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Message-Id: <20250212-apple-cpmu-v1-9-f8c7f2ac1743@gmail.com>
Date: Wed, 12 Feb 2025 00:07:30 +0800
From: Nick Chan <towinchenmi@...il.com>
To: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>
Cc: Marc Zyngier <maz@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-perf-users@...r.kernel.org, devicetree@...r.kernel.org,
asahi@...ts.linux.dev, linux-kernel@...r.kernel.org,
Nick Chan <towinchenmi@...il.com>
Subject: [PATCH 09/10] drivers/perf: apple_m1: Add Apple A10/A10X/T2
Support
Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs.
Signed-off-by: Nick Chan <towinchenmi@...il.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 126 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 1575f8eda874345eb56c00f8243833308c63a84a..2eafcb1bfcf6bf4b57a939c5470552cba81e7758 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -391,6 +391,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] = {
[A9_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7,
};
+enum a10_pmu_events {
+ A10_PMU_PERFCTR_RETIRE_UOP = 0x1,
+ A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
+ A10_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
+ A10_PMU_PERFCTR_L2C_AGENT_LD = 0x1a,
+ A10_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b,
+ A10_PMU_PERFCTR_L2C_AGENT_ST = 0x1c,
+ A10_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d,
+ A10_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
+ A10_PMU_PERFCTR_MAP_REWIND = 0x75,
+ A10_PMU_PERFCTR_MAP_STALL = 0x76,
+ A10_PMU_PERFCTR_MAP_INT_UOP = 0x7c,
+ A10_PMU_PERFCTR_MAP_LDST_UOP = 0x7d,
+ A10_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e,
+ A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
+ A10_PMU_PERFCTR_INST_ALL = 0x8c,
+ A10_PMU_PERFCTR_INST_BRANCH = 0x8d,
+ A10_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
+ A10_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
+ A10_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
+ A10_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
+ A10_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
+ A10_PMU_PERFCTR_INST_INT_LD = 0x95,
+ A10_PMU_PERFCTR_INST_INT_ST = 0x96,
+ A10_PMU_PERFCTR_INST_INT_ALU = 0x97,
+ A10_PMU_PERFCTR_INST_SIMD_LD = 0x98,
+ A10_PMU_PERFCTR_INST_SIMD_ST = 0x99,
+ A10_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
+ A10_PMU_PERFCTR_INST_LDST = 0x9b,
+ A10_PMU_PERFCTR_INST_BARRIER = 0x9c,
+ A10_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A10_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
+ A10_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
+ A10_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
+ A10_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
+ A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
+ A10_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
+ A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3,
+ A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
+ A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
+ A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
+ A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
+ A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
+ A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
+ A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
+ A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
+ A10_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3,
+ A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
+ A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6,
+ A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb,
+ A10_PMU_PERFCTR_FETCH_RESTART = 0xde,
+ A10_PMU_PERFCTR_ST_NT_UOP = 0xe5,
+ A10_PMU_PERFCTR_LD_NT_UOP = 0xe6,
+ A10_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A10_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A10_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A10_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
+ A10_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
+ A10_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A10_PMU_CFG_COUNT_USER = BIT(8),
+ A10_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A10_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A10_PMU_PERFCTR_RETIRE_UOP] = BIT(7),
+ [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A10_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
+ [A10_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_INT_ALU] = BIT(7),
+ [A10_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7),
+ [A10_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
+ [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
+ [A10_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
+ [A10_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
+ [A10_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
+ [A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -864,6 +973,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity);
}
+static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -1033,6 +1148,16 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu)
return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, A7_PMU_NR_COUNTERS);
}
+static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_fusion_pmu";
+ cpu_pmu->get_event_idx = a10_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = a7_pmu_start;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -1078,6 +1203,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, },
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
+ { .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, },
{ .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, },
{ .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, },
{ .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
--
2.48.1
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