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Message-Id: <20250212-apple-cpmu-v1-10-f8c7f2ac1743@gmail.com>
Date: Wed, 12 Feb 2025 00:07:31 +0800
From: Nick Chan <towinchenmi@...il.com>
To: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>
Cc: Marc Zyngier <maz@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-perf-users@...r.kernel.org, devicetree@...r.kernel.org,
asahi@...ts.linux.dev, linux-kernel@...r.kernel.org,
Nick Chan <towinchenmi@...il.com>
Subject: [PATCH 10/10] drivers/perf: apple_m1: Add Apple A11 Support
Add support for the CPU PMU found attached to the performance and
efficiency cores of the Apple A11 SoCs. This PMU can deliver its
interrupt via IRQ or FIQ. Use FIQ as that is faster.
Signed-off-by: Nick Chan <towinchenmi@...il.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 135 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 2eafcb1bfcf6bf4b57a939c5470552cba81e7758..254eb8e08906c2f0366c27f2089095ecd2fc7adb 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -500,6 +500,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = {
[A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
};
+enum a11_pmu_events {
+ A11_PMU_PERFCTR_RETIRE_UOP = 0x1,
+ A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
+ A11_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
+ A11_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
+ A11_PMU_PERFCTR_MAP_REWIND = 0x75,
+ A11_PMU_PERFCTR_MAP_STALL = 0x76,
+ A11_PMU_PERFCTR_MAP_INT_UOP = 0x7c,
+ A11_PMU_PERFCTR_MAP_LDST_UOP = 0x7d,
+ A11_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e,
+ A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
+ A11_PMU_PERFCTR_INST_A32 = 0x8a,
+ A11_PMU_PERFCTR_INST_T32 = 0x8b,
+ A11_PMU_PERFCTR_INST_ALL = 0x8c,
+ A11_PMU_PERFCTR_INST_BRANCH = 0x8d,
+ A11_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
+ A11_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
+ A11_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
+ A11_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
+ A11_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
+ A11_PMU_PERFCTR_INST_INT_LD = 0x95,
+ A11_PMU_PERFCTR_INST_INT_ST = 0x96,
+ A11_PMU_PERFCTR_INST_INT_ALU = 0x97,
+ A11_PMU_PERFCTR_INST_SIMD_LD = 0x98,
+ A11_PMU_PERFCTR_INST_SIMD_ST = 0x99,
+ A11_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
+ A11_PMU_PERFCTR_INST_LDST = 0x9b,
+ A11_PMU_PERFCTR_INST_BARRIER = 0x9c,
+ A11_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A11_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
+ A11_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
+ A11_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
+ A11_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
+ A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
+ A11_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
+ A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3,
+ A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
+ A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
+ A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
+ A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
+ A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
+ A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
+ A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
+ A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
+ A11_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3,
+ A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
+ A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6,
+ A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb,
+ A11_PMU_PERFCTR_FETCH_RESTART = 0xde,
+ A11_PMU_PERFCTR_ST_NT_UOP = 0xe5,
+ A11_PMU_PERFCTR_LD_NT_UOP = 0xe6,
+ A11_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A11_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A11_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A11_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
+ A11_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
+ A11_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A11_PMU_CFG_COUNT_USER = BIT(8),
+ A11_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A11_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A11_PMU_PERFCTR_RETIRE_UOP] = BIT(7),
+ [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A11_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
+ [A11_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_INT_ALU] = BIT(7),
+ [A11_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7),
+ [A11_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
+ [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
+ [A11_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
+ [A11_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
+ [A11_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
+ [A11_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -979,6 +1086,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity);
}
+static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -1158,6 +1271,26 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu)
return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS);
}
+static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_monsoon_pmu";
+ cpu_pmu->get_event_idx = a11_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS);
+}
+
+static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_mistral_pmu";
+ cpu_pmu->get_event_idx = a11_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
+ return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -1204,6 +1337,8 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
{ .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, },
+ { .compatible = "apple,monsoon-pmu", .data = a11_pmu_monsoon_init, },
+ { .compatible = "apple,mistral-pmu", .data = a11_pmu_mistral_init, },
{ .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, },
{ .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, },
{ .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
--
2.48.1
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