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Message-ID: <20250211105603.195905-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 11 Feb 2025 10:56:02 +0000
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH] clk: renesas: rzg2l-cpg: Update error message
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Update the error message in `rzg2l_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `CLK_ON_R(reg)` offset and the corresponding
`clk` name (`%pC`). This enhances readability and aids in debugging
clock enable failures.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
drivers/clk/renesas/rzg2l-cpg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 91928db411dc..a6b87cc66cbb 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1239,8 +1239,8 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
value & bitmask, 0, 10);
if (error)
- dev_err(dev, "Failed to enable CLK_ON %p\n",
- priv->base + CLK_ON_R(reg));
+ dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n",
+ CLK_ON_R(reg), hw->clk);
return error;
}
--
2.43.0
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