linux-kernel - Re: [PATCH] irqchip/qcom-pdc: Workaround hardware register bug on X1E80100

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Message-ID: <Z64oi_UVsJAxmm28@hovoldconsulting.com>
Date: Thu, 13 Feb 2025 18:14:51 +0100
From: Johan Hovold <johan@...nel.org>
To: Stephan Gerhold <stephan.gerhold@...aro.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>,
	Rajendra Nayak <quic_rjendra@...cinc.com>,
	Maulik Shah <quic_mkshah@...cinc.com>,
	Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
	Abel Vesa <abel.vesa@...aro.org>, linux-arm-msm@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] irqchip/qcom-pdc: Workaround hardware register bug on
 X1E80100

On Thu, Feb 13, 2025 at 06:04:00PM +0100, Stephan Gerhold wrote:
> On X1E80100, there is a hardware bug in the register logic of the
> IRQ_ENABLE_BANK register. While read accesses work on the normal address,
> all write accesses must be made to a shifted address. Without a workaround
> for this, the wrong interrupt gets enabled in the PDC and it is impossible
> to wakeup from deep suspend (CX collapse).
> 
> This has not caused problems so far, because the deep suspend state was not
> enabled. We need a workaround now since work is ongoing to fix this.
> 
> Introduce a workaround for the problem by matching the qcom,x1e80100-pdc
> compatible and shift the write address by the necessary offset.
> 
> Signed-off-by: Stephan Gerhold <stephan.gerhold@...aro.org>

I've been running with this patch for a while now and it allows me to
wake up from deep suspend on the X1E CRD using the power button (or
GPIO interrupts with further patches):

Tested-by: Johan Hovold <johan+linaro@...nel.org>

Johan