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Message-ID: <9f2531dd-6ee3-4e71-9b29-4cdf9da410a6@amd.com>
Date: Fri, 14 Feb 2025 13:46:59 -0600
From: "Bowman, Terry" <terry.bowman@....com>
To: Dan Williams <dan.j.williams@...el.com>, linux-cxl@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
nifan.cxl@...il.com, dave@...olabs.net, jonathan.cameron@...wei.com,
dave.jiang@...el.com, alison.schofield@...el.com, vishal.l.verma@...el.com,
bhelgaas@...gle.com, mahesh@...ux.ibm.com, ira.weiny@...el.com,
oohall@...il.com, Benjamin.Cheatham@....com, rrichter@....com,
nathan.fontenot@....com, Smita.KoralahalliChannabasappa@....com,
lukas@...ner.de, ming.li@...omail.com, PradeepVineshReddy.Kodamati@....com
Subject: Re: [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream Switch Port RAS
registers
On 2/11/2025 8:00 PM, Dan Williams wrote:
> Terry Bowman wrote:
>> Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers.
>>
>> Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a
>> pointer to the CXL Upstream Port's mapped RAS registers.
>>
>> Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS
>> register mapping. This is similar to the existing
>> cxl_dport_init_ras_reporting() but for USP devices.
>>
>> The USP may have multiple downstream endpoints. Before mapping RAS
>> registers check if the registers are already mapped.
> Yes, now this sharing makes sense, but the ras_init_mutex +
> cxl_init_ep_ports_aer() approach to solving it is broken.
>
>> Introduce a mutex for synchronizing accesses to the cached RAS
>> mapping.
> In this case, especially for VH configs, you should just be able to map
> the RAS registers once from cxl_endpoint_port_probe(). That will
> naturally only be called once when the first endpoint arrives, and will
> never be torn down until the last cxl_detach_ep() event triggers
> delete_switch_port().
There is still RPs and USPs that will be called for mapping more than once,
right? This will require synchronization, right?
Terry
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