[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <6b52c51f4046dda5d9aa3726e9be51c746e9c623.camel@mediatek.com>
Date: Fri, 14 Feb 2025 07:41:01 +0000
From: Chun-Jen Tseng (曾俊仁)
<Chun-Jen.Tseng@...iatek.com>
To: "viresh.kumar@...aro.org" <viresh.kumar@...aro.org>, "AngeloGioacchino Del
Regno" <angelogioacchino.delregno@...labora.com>, "rafael@...nel.org"
<rafael@...nel.org>, "myungjoo.ham@...sung.com" <myungjoo.ham@...sung.com>,
"kyungmin.park@...sung.com" <kyungmin.park@...sung.com>,
"cw00.choi@...sung.com" <cw00.choi@...sung.com>, "matthias.bgg@...il.com"
<matthias.bgg@...il.com>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>, "linux-pm@...r.kernel.org"
<linux-pm@...r.kernel.org>, Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/4] cpufreq: mediatek: CCI support SoC , the
transition_delay set to 10 ms
On Thu, 2024-11-14 at 11:22 +0100, AngeloGioacchino Del Regno wrote:
hi Angelo,
Thanks your review and recommendation.
I will fix this issue on next patch.
BRs,
Mark Tseng
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Il 08/11/24 07:39, Mark Tseng ha scritto:
> > SoC with CCI architecture should set transition_delay to 10 ms
> > because
> > cpufreq need to call devfreq notifier in async mode. if delay less
> > than
> > 10 ms, it may get wrong OPP-level in devfreq passive governor.
> >
>
> This means that MediaTek SoCs can change their CPU frequency once
> every
> 10 milliseconds?!?!?!
>
> I don't think that's really the case.
>
> Besides, are you aware that this will have a *huge* impact on either
> power
> consumption or performance?
> We're going from a bunch of microseconds to *multiple* milliseconds
> here.
>
> Regards,
> Angelo
>
Powered by blists - more mailing lists