linux-kernel - Re: [PATCH v2 1/4] KVM: arm64: Allow userspace to change MIDR

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Message-ID: <87v7tb17os.wl-maz@kernel.org>
Date: Sat, 15 Feb 2025 16:41:55 +0000
From: Marc Zyngier <maz@...nel.org>
To: luoyonggang@...il.com
Cc: Oliver Upton <oliver.upton@...ux.dev>,	Sebastian Ott <sebott@...hat.com>,	Joey Gouly <joey.gouly@....com>,	Suzuki K Poulose <suzuki.poulose@....com>,	Zenghui Yu <yuzenghui@...wei.com>,	Catalin Marinas <catalin.marinas@....com>,	Will Deacon <will@...nel.org>,	Shameer Kolothum <shameerali.kolothum.thodi@...wei.com>,	Cornelia Huck <cohuck@...hat.com>,	Eric Auger <eric.auger@...hat.com>,	linux-arm-kernel@...ts.infradead.org,	kvmarm@...ts.linux.dev,	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/4] KVM: arm64: Allow userspace to change MIDR_EL1

On Sat, 15 Feb 2025 16:16:44 +0000,
"罗勇刚(Yonggang Luo)" <luoyonggang@...il.com> wrote:
> 
> On Sat, Feb 15, 2025 at 6:15 PM Oliver Upton <oliver.upton@...ux.dev> wrote:
> >
> > Hi Sebastian,
> >
> > On Tue, Feb 11, 2025 at 03:39:07PM +0100, Sebastian Ott wrote:
> > > +static int set_id_reg_non_ftr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
> > > +                           u64 val)
> > > +{
> > > +     u32 id = reg_to_encoding(rd);
> > > +     int ret;
> > > +
> > > +     mutex_lock(&vcpu->kvm->arch.config_lock);
> >
> > There's quite a few early outs, guard() might be a better fit than
> > explicitly dropping the lock.
> >
> > > +     /*
> > > +      * Since guest access to MIDR_EL1 is not trapped
> > > +      * set up VPIDR_EL2 to hold the MIDR_EL1 value.
> > > +      */
> > > +     if (id == SYS_MIDR_EL1)
> > > +             write_sysreg(val, vpidr_el2);
> >
> > This is problematic for a couple reasons:
> >
> >  - If the kernel isn't running at EL2, VPIDR_EL2 is undefined
> >
> >  - VPIDR_EL2 needs to be handled as part of the vCPU context, not
> >    written to without a running vCPU. What would happen if two vCPUs
> >    have different MIDR values?
> >
> > Here's a new diff with some hacks thrown in to handle VPIDR_EL2
> > correctly. Very lightly tested :)
> 
> Thans, I am also faced this issue, but other than this, I am also
> facing a issue, after updating
> MIDR_EL1, The CP15 register MIDR for aarch32 not updated.
> The instruction is `MRC p15,0,<Rt>,c0,c0,0    ; Read CP15 Main ID Register` from
> https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Protected-Memory-System-Architecture--PMSA-/CP15-registers-for-a-PMSA-implementation/c0--Main-ID-Register--MIDR-
> 
> The value of this instruction is not updated

How do you determine that MIDR isn't updated? How do you update the
userspace view?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.