| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAE2XoE9=hjP+qpsy+FcYcSDectDajiXjtcMCVpacSo4cFOo=tQ@mail.gmail.com>
Date: Sun, 16 Feb 2025 03:04:20 +0800
From: 罗勇刚(Yonggang Luo) <luoyonggang@...il.com>
To: Marc Zyngier <maz@...nel.org>
Cc: Oliver Upton <oliver.upton@...ux.dev>, Sebastian Ott <sebott@...hat.com>,
Joey Gouly <joey.gouly@....com>, Suzuki K Poulose <suzuki.poulose@....com>,
Zenghui Yu <yuzenghui@...wei.com>, Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Shameer Kolothum <shameerali.kolothum.thodi@...wei.com>,
Cornelia Huck <cohuck@...hat.com>, Eric Auger <eric.auger@...hat.com>,
linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/4] KVM: arm64: Allow userspace to change MIDR_EL1
>
> How do you determine that MIDR isn't updated? How do you update the
> userspace view?
>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
The testing code is at
https://github.com/lygstate/arm64-kvm-hello-world/tree/midr/bare-metal-aarch32-qemu
qemu changes:
```
>From 543f2f656952ab01509025b79d0198736ef68231 Mon Sep 17 00:00:00 2001
From: Yonggang Luo <luoyonggang@...il.com>
Date: Sun, 16 Feb 2025 02:57:44 +0800
Subject: [PATCH] Add support midr options for arm virt machine
---
hw/arm/virt.c | 20 ++++++++++++++++++++
include/hw/arm/virt.h | 1 +
target/arm/kvm.c | 21 +++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4a5a9666e9..5ba690a70d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2236,6 +2236,10 @@ static void machvirt_init(MachineState *machine)
object_property_set_int(cpuobj, "mp-affinity",
possible_cpus->cpus[n].arch_id, NULL);
+ if (vms->midr) {
+ object_property_set_int(cpuobj, "midr", vms->midr, NULL);
+ }
+
cs = CPU(cpuobj);
cs->cpu_index = n;
@@ -3348,6 +3352,17 @@ static const TypeInfo virt_machine_info = {
},
};
+static char * virt_get_midr(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+ return g_strdup_printf("0x%08x", vms->midr);
+}
+static void virt_set_midr(Object *obj, const char *value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+ vms->midr = strtoul(value, 0, 0);
+}
+
static void machvirt_machine_init(void)
{
type_register_static(&virt_machine_info);
@@ -3356,6 +3371,11 @@ type_init(machvirt_machine_init);
static void virt_machine_10_0_options(MachineClass *mc)
{
+ ObjectClass *oc = &mc->parent_class;
+ object_class_property_add_str(oc, "midr", virt_get_midr,
+ virt_set_midr);
+ object_class_property_set_description(oc, "midr",
+ "Set MDIR value for VIRT machine");
}
DEFINE_VIRT_MACHINE_AS_LATEST(10, 0)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index c8e94e6aed..fe200b0d76 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -179,6 +179,7 @@ struct VirtMachineState {
PCIBus *bus;
char *oem_id;
char *oem_table_id;
+ uint32_t midr;
bool ns_el2_virt_timer_irq;
};
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index da30bdbb23..577eaee505 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -1873,6 +1873,7 @@ static int kvm_arm_sve_set_vls(ARMCPU *cpu)
}
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
+#define ARM_CPU_ID_MIDR_EL1 3, 0, 0, 0, 0
int kvm_arch_init_vcpu(CPUState *cs)
{
@@ -1920,6 +1921,26 @@ int kvm_arch_init_vcpu(CPUState *cs)
return ret;
}
+ {
+ uint64_t midr = cpu->midr;
+ ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MIDR_EL1), &midr);
+ if (ret) {
+ return ret;
+ }
+ printf("Get MIDR EL1 origin:0x%08x\n", (uint32_t)midr);
+ midr = cpu->midr;
+ ret = kvm_set_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MIDR_EL1), &midr);
+ printf("Set MIDR EL1:0x%08x\n", (uint32_t)midr);
+ if (ret) {
+ return ret;
+ }
+ ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MIDR_EL1), &midr);
+ printf("Get MIDR EL1:0x%08x\n", (uint32_t)midr);
+ if (ret) {
+ return ret;
+ }
+ }
+
if (cpu_isar_feature(aa64_sve, cpu)) {
ret = kvm_arm_sve_set_vls(cpu);
if (ret) {
--
2.47.1.windows.1
```
The TCG running result:
```
/home/lygstate/work/qemu/build:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
/home/lygstate/work/qemu/build/qemu-system-aarch64
+ qemu-system-aarch64 -cpu cortex-a15 -accel tcg,thread=multi -m 1024M
-smp 1 -M virt,gic-version=3,midr=0x412fd050 -nographic -monitor none
-serial stdio -kernel
/home/lygstate/work/debian/arm64-kvm-hello-world/bare-metal-aarch32-qemu/hello_world.elf
Hello World midr:0x412fd050
```
The KVM running result:
```
/home/lygstate/work/qemu/build:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
/home/lygstate/work/qemu/build/qemu-system-aarch64
+ qemu-system-aarch64 -cpu host,aarch64=off -accel kvm -m 1024M -smp 1
-M virt,gic-version=3,midr=0x412fd050 -nographic -monitor none -serial
stdio -kernel /home/lygstate/work/debian/arm64-kvm-hello-world/bare-metal-aarch32-qemu/hello_world.elf
Get MIDR EL1 origin:0x410fd083
Set MIDR EL1:0x412fd050
Get MIDR EL1:0x412fd050
Hello World midr:0x410fd083
```
According to this, the MIDR EL1 is updated properly, but the MIDR for
aarch32 is not updated, and I don't know how to hook the update for
MIDR for aarch32
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
Powered by blists - more mailing lists