linux-kernel - [PATCH V3 1/2] schemas: pci: bridge: Document PCI L0s & L1 entry delay

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Message-Id: <20250216014510.3990613-2-krishna.chundru@oss.qualcomm.com>
Date: Sun, 16 Feb 2025 07:15:09 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: andersson@...nel.org, robh@...nel.org, dmitry.baryshkov@...aro.org,
        manivannan.sadhasivam@...aro.org, krzk@...nel.org, helgaas@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        lpieralisi@...nel.org, kw@...ux.com, conor+dt@...nel.org,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree-spec@...r.kernel.org, quic_vbadigan@...cinc.com,
        Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Subject: [PATCH V3 1/2] schemas: pci: bridge: Document PCI L0s & L1 entry delay

Some controllers and endpoints provide provision to program the entry
delays of L0s & L1 which will allow the link to enter L0s & L1 more
aggressively to save power.

These values needs to be programmed before link training.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
---
 dtschema/schemas/pci/pci-bus-common.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index 94b648f..a9309af 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -150,6 +150,12 @@ properties:
     description: Disables ASPM L0s capability
     type: boolean
 
+  aspm-l0s-entry-delay-ns:
+    description: ASPM L0s entry delay
+
+  aspm-l1-entry-delay-ns:
+    description: ASPM L1 entry delay
+
   vpcie12v-supply:
     description: 12v regulator phandle for the slot
 
-- 
2.34.1