linux-kernel - Re: [PATCH] arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX

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Message-ID: <20250216010814.375313-1-liujianfeng1994@gmail.com>
Date: Sun, 16 Feb 2025 09:08:14 +0800
From: Jianfeng Liu <liujianfeng1994@...il.com>
To: sebastian.reichel@...labora.com
Cc: conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	heiko@...ech.de,
	krzk+dt@...nel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	linux-rockchip@...ts.infradead.org,
	liujianfeng1994@...il.com,
	piotr.oniszczuk@...il.com,
	robh@...nel.org,
	sfr@...b.auug.org.au
Subject: Re: [PATCH] arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX

Hi,

Sat, 15 Feb 2025 23:22:27 +0100, Sebastian Reichel wrote:
>&hdptxphy_hdmi0? That looks like a downstream thing and also for the
>wrong port?

You are right. I was refering to the patch of rock5b from mailing list[1],
in which there is "&hdptxphy_hdmi0" so I assumed this port is merged
upstream.

Although ROCK 5 ITX only uses hdmi1, vop need &hdptxphy0 for pll clk, so
this node is necessary if we don't change the vop clocks at board level
devicetree.

I just notice that there is a new patch series[2] to let phy of hdmi1
provide clk. I have to add both hdptxphy0 and hdptxphy1 based on this
series, or I can only add hdptxphy1 and change the vop clk like:

&vop {
	clocks = <&cru ACLK_VOP>,
		 <&cru HCLK_VOP>,
		 <&cru DCLK_VOP0>,
		 <&cru DCLK_VOP1>,
		 <&cru DCLK_VOP2>,
		 <&cru DCLK_VOP3>,
		 <&cru PCLK_VOP_ROOT>,
		 <&hdptxphy1>;
	clock-names = "aclk",
		      "hclk",
		      "dclk_vp0",
		      "dclk_vp1",
		      "dclk_vp2",
		      "dclk_vp3",
		      "pclk_vop",
		      "pll_hdmiphy1";
};

[1] https://lore.kernel.org/all/20241211-rk3588-hdmi1-v2-4-02cdca22ff68@collabora.com/
[2] https://lore.kernel.org/all/20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com/

Best regards,
Jianfeng