linux-kernel - Re: [PATCH v2 12/17] cpufreq/amd-pstate: Cache CPPC request in shared mem case too

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Message-ID: <Z7M/h84bi1FIrPqE@BLRRASHENOY1.amd.com>
Date: Mon, 17 Feb 2025 19:24:15 +0530
From: "Gautham R. Shenoy" <gautham.shenoy@....com>
To: Mario Limonciello <superm1@...nel.org>
Cc: Perry Yuan <perry.yuan@....com>,
	Dhananjay Ugwekar <Dhananjay.Ugwekar@....com>,
	"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
	"open list:CPU FREQUENCY SCALING FRAMEWORK" <linux-pm@...r.kernel.org>,
	Mario Limonciello <mario.limonciello@....com>
Subject: Re: [PATCH v2 12/17] cpufreq/amd-pstate: Cache CPPC request in
 shared mem case too

On Fri, Feb 14, 2025 at 06:52:39PM -0600, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@....com>
> 
> In order to prevent a potential write for shmem_update_perf()
> cache the request into the cppc_req_cached variable normally only
> used for the MSR case.
> 
> This adds symmetry into the code and potentially avoids extra writes.
> 
> Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@....com>
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  drivers/cpufreq/amd-pstate.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 0a7e69fd32dbf..9517da9b7e692 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -496,6 +496,8 @@ static int shmem_update_perf(struct amd_cpudata *cpudata, u8 min_perf,
>  			     u8 des_perf, u8 max_perf, u8 epp, bool fast_switch)
>  {
>  	struct cppc_perf_ctrls perf_ctrls;
> +	u64 value, prev;
> +	int ret;
>  
>  	if (cppc_state == AMD_PSTATE_ACTIVE) {
>  		int ret = shmem_set_epp(cpudata, epp);
> @@ -504,11 +506,29 @@ static int shmem_update_perf(struct amd_cpudata *cpudata, u8 min_perf,
>  			return ret;
>  	}
>  
> +	value = prev = READ_ONCE(cpudata->cppc_req_cached);
> +
> +	value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK |
> +		   AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK);
> +	value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf);
> +	value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf);
> +	value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf);
> +	value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);


Perhaps this can be further simplified in the future using a new macro
FIELD_SET(var, mask, val) where

#define FIELD_SET(var, mask, val)     var = ((var) & ~(mask)) | FIELD_PREP(mask, val))

For this patch,

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>

-- 
Thanks and Regards
gautham.