linux-kernel - Re: [PATCH v2 11/17] cpufreq/amd-pstate: Replace all AMD_CPPC

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Message-ID: <Z7M+Kd4Ul0k5r3O4@BLRRASHENOY1.amd.com>
Date: Mon, 17 Feb 2025 19:18:25 +0530
From: "Gautham R. Shenoy" <gautham.shenoy@....com>
To: Mario Limonciello <superm1@...nel.org>
Cc: Perry Yuan <perry.yuan@....com>,
	Dhananjay Ugwekar <Dhananjay.Ugwekar@....com>,
	"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
	"open list:CPU FREQUENCY SCALING FRAMEWORK" <linux-pm@...r.kernel.org>,
	Mario Limonciello <mario.limonciello@....com>
Subject: Re: [PATCH v2 11/17] cpufreq/amd-pstate: Replace all AMD_CPPC_*
 macros with masks

On Fri, Feb 14, 2025 at 06:52:38PM -0600, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@....com>
> 
> Bitfield masks are easier to follow and less error prone.


LGTM.

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>




> 
> Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@....com>
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
> v2:
>  * Add a comment in msr-index.h
>  * Pick up tag
> ---
>  arch/x86/include/asm/msr-index.h | 20 +++++++++++---------
>  arch/x86/kernel/acpi/cppc.c      |  2 +-
>  drivers/cpufreq/amd-pstate-ut.c  |  8 ++++----
>  drivers/cpufreq/amd-pstate.c     | 16 ++++++----------
>  4 files changed, 22 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 3eadc4d5de837..4bb87884998a0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -700,15 +700,17 @@
>  #define MSR_AMD_CPPC_REQ		0xc00102b3
>  #define MSR_AMD_CPPC_STATUS		0xc00102b4
>  
> -#define AMD_CPPC_LOWEST_PERF(x)		(((x) >> 0) & 0xff)
> -#define AMD_CPPC_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
> -#define AMD_CPPC_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
> -#define AMD_CPPC_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
> -
> -#define AMD_CPPC_MAX_PERF(x)		(((x) & 0xff) << 0)
> -#define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
> -#define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
> -#define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
> +/* Masks for use with MSR_AMD_CPPC_CAP1 */
> +#define AMD_CPPC_LOWEST_PERF_MASK	GENMASK(7, 0)
> +#define AMD_CPPC_LOWNONLIN_PERF_MASK	GENMASK(15, 8)
> +#define AMD_CPPC_NOMINAL_PERF_MASK	GENMASK(23, 16)
> +#define AMD_CPPC_HIGHEST_PERF_MASK	GENMASK(31, 24)
> +
> +/* Masks for use with MSR_AMD_CPPC_REQ */
> +#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
> +#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
> +#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
> +#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
>  
>  /* AMD Performance Counter Global Status and Control MSRs */
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
> diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
> index f96053c305c61..77bfb846490c0 100644
> --- a/arch/x86/kernel/acpi/cppc.c
> +++ b/arch/x86/kernel/acpi/cppc.c
> @@ -151,7 +151,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
>  		if (ret)
>  			goto out;
>  
> -		val = AMD_CPPC_HIGHEST_PERF(val);
> +		val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
>  	} else {
>  		ret = cppc_get_highest_perf(cpu, &val);
>  		if (ret)
> diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
> index 9db20ac357042..067e9e325102e 100644
> --- a/drivers/cpufreq/amd-pstate-ut.c
> +++ b/drivers/cpufreq/amd-pstate-ut.c
> @@ -142,10 +142,10 @@ static int amd_pstate_ut_check_perf(u32 index)
>  				return ret;
>  			}
>  
> -			highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
> -			nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
> -			lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
> -			lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
> +			highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
> +			nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
> +			lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
> +			lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>  		}
>  
>  		cur_perf = READ_ONCE(cpudata->perf);
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index e5983e5c77ba2..0a7e69fd32dbf 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -89,11 +89,6 @@ static bool cppc_enabled;
>  static bool amd_pstate_prefcore = true;
>  static struct quirk_entry *quirks;
>  
> -#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
> -#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
> -#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
> -#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
> -
>  /*
>   * AMD Energy Preference Performance (EPP)
>   * The EPP is used in the CCLK DPM controller to drive
> @@ -439,12 +434,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata)
>  
>  	perf.highest_perf = numerator;
>  	perf.max_limit_perf = numerator;
> -	perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
> -	perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
> -	perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
> -	perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
> +	perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
> +	perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
> +	perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
> +	perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>  	WRITE_ONCE(cpudata->perf, perf);
> -	WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
> +	WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
> +
>  	return 0;
>  }
>  
> -- 
> 2.43.0
> 

-- 
Thanks and Regards
gautham.