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Message-ID: <CY8PR11MB713471B0264788235FA9079389FA2@CY8PR11MB7134.namprd11.prod.outlook.com>
Date: Tue, 18 Feb 2025 13:27:04 +0000
From: "Zhuo, Qiuxu" <qiuxu.zhuo@...el.com>
To: Yazen Ghannam <yazen.ghannam@....com>, "x86@...nel.org" <x86@...nel.org>,
	"Luck, Tony" <tony.luck@...el.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
	"Smita.KoralahalliChannabasappa@....com"
	<Smita.KoralahalliChannabasappa@....com>
Subject: RE: [PATCH v2 15/16] x86/mce/amd: Support SMCA Corrected Error
 Interrupt

> From: Yazen Ghannam <yazen.ghannam@....com>
> [...]
> --- a/arch/x86/kernel/cpu/mce/amd.c
> +++ b/arch/x86/kernel/cpu/mce/amd.c
> @@ -306,6 +306,11 @@ static void smca_configure(unsigned int bank,
> unsigned int cpu)
>  			high |= BIT(5);
>  		}
> 

Do you think it would be better to have some comments on the thresholding 
interrupt here (as the bits 10/8 look like magic numbers), similar to the 
comments above for the deferred interrupt?

> +		if ((low & BIT(10)) && data->thr_intr_en) {
> +			__set_bit(bank, data->thr_intr_banks);
> +			high |= BIT(8);
> +		}
> +
> [...]

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