linux-kernel - RE: [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms

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Message-ID: <CY8PR11MB7134F91FCEB3BA8D2CFE4DE689FA2@CY8PR11MB7134.namprd11.prod.outlook.com>
Date: Tue, 18 Feb 2025 13:51:27 +0000
From: "Zhuo, Qiuxu" <qiuxu.zhuo@...el.com>
To: Yazen Ghannam <yazen.ghannam@....com>, "x86@...nel.org" <x86@...nel.org>,
	"Luck, Tony" <tony.luck@...el.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
	"Smita.KoralahalliChannabasappa@....com"
	<Smita.KoralahalliChannabasappa@....com>
Subject: RE: [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms

> From: Yazen Ghannam <yazen.ghannam@....com>
> Sent: Friday, February 14, 2025 12:46 AM
> To: x86@...nel.org; Luck, Tony <tony.luck@...el.com>
> Cc: linux-kernel@...r.kernel.org; linux-edac@...r.kernel.org;
> Smita.KoralahalliChannabasappa@....com; Yazen Ghannam
> <yazen.ghannam@....com>
> Subject: [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms
> 
> From: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>
> 
> Extend the logic of handling CMCI storms to AMD threshold interrupts.
> 
> Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU
> and per bank. But, unlike CMCI, do not set thresholds and reduce interrupt
> rate on a storm. Rather, disable the interrupt on the corresponding CPU and
> bank. Re-enable back the interrupts if enough consecutive polls of the bank
> show no corrected errors (30, as programmed by Intel).
> 
> Turning off the threshold interrupts would be a better solution on AMD
> systems as other error severities will still be handled even if the threshold
> interrupts are disabled.
> 
> [Tony: Small tweak because mce_handle_storm() isn't a pointer now]
> [Yazen: Rebase and simplify]
> 
> Signed-off-by: Smita Koralahalli
> <Smita.KoralahalliChannabasappa@....com>
> Signed-off-by: Tony Luck <tony.luck@...el.com>
> Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>

LGTM.

    Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>