linux-kernel - RE: [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CY8PR11MB7134A549EDB172C3FB87233989FA2@CY8PR11MB7134.namprd11.prod.outlook.com>
Date: Tue, 18 Feb 2025 06:42:52 +0000
From: "Zhuo, Qiuxu" <qiuxu.zhuo@...el.com>
To: Yazen Ghannam <yazen.ghannam@....com>, "x86@...nel.org" <x86@...nel.org>,
	"Luck, Tony" <tony.luck@...el.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
	"Smita.KoralahalliChannabasappa@....com"
	<Smita.KoralahalliChannabasappa@....com>
Subject: RE: [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling

> From: Yazen Ghannam <yazen.ghannam@....com>
> Sent: Friday, February 14, 2025 12:46 AM
> To: x86@...nel.org; Luck, Tony <tony.luck@...el.com>
> Cc: linux-kernel@...r.kernel.org; linux-edac@...r.kernel.org;
> Smita.KoralahalliChannabasappa@....com; Yazen Ghannam
> <yazen.ghannam@....com>
> Subject: [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling
> 
> AMD systems optionally support an MCA thresholding interrupt. The interrupt
> should be used as another signal to trigger MCA polling. This is similar to how
> the Intel Corrected Machine Check interrupt (CMCI) is handled.
> 
> AMD MCA thresholding is managed using the MCA_MISC registers within an
> MCA bank. The OS will need to modify the hardware error count field in order
> to reset the threshold limit and rearm the interrupt. Management of the
> MCA_MISC register should be done as a follow up to the basic MCA polling

s/follow up/follow-up

> flow. It should not be the main focus of the interrupt handler.
> 
> Furthermore, future systems will have the ability to send an MCA
> thresholding interrupt to the OS even when the OS does not manage the
> feature, i.e. MCA_MISC registers are Read-as-Zero/Locked.
> 
> Call the common MCA polling function when handling the MCA thresholding
> interrupt. This will allow the OS to find any valid errors whether or not the
> MCA thresholding feature is OS-managed. Also, this allows the common MCA
> polling options and kernel parameters to apply to AMD systems.
> 
> Add a callback to the MCA polling function to check and reset any threshold
> blocks that have reached their threshold limit.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>

Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com>