linux-kernel - Re: [PATCH V3 0/2] schemas: pci: bridge: Document PCI L0s & L1 entry delay and N

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Message-ID: <20250219194923.GA2776564-robh@kernel.org>
Date: Wed, 19 Feb 2025 13:49:23 -0600
From: Rob Herring <robh@...nel.org>
To: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Cc: andersson@...nel.org, dmitry.baryshkov@...aro.org,
	manivannan.sadhasivam@...aro.org, krzk@...nel.org,
	helgaas@...nel.org, linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org, lpieralisi@...nel.org, kw@...ux.com,
	conor+dt@...nel.org, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, devicetree-spec@...r.kernel.org,
	quic_vbadigan@...cinc.com
Subject: Re: [PATCH V3 0/2] schemas: pci: bridge: Document PCI L0s & L1 entry
 delay and N_FTS

On Sun, Feb 16, 2025 at 07:15:08AM +0530, Krishna Chaitanya Chundru wrote:
> Some controllers and endpoints provide provision to program the entry
> delays of L0s & L1 which will allow the link to enter L0s & L1 more
> aggressively to save power.
> 
> Per PCIe r6.0, sec 4.2.5.1, during Link training, a PCIe component
> captures the N_FTS value it receives.  Per 4.2.5.6, when
> transitioning the Link from L0s to L0, it must transmit N_FTS Fast
> Training Sequences to enable the receiver to obtain bit and Symbol
> lock.
> 
> Components may have device-specific ways to configure N_FTS values
> to advertise during Link training.  Define an n-fts array with an
> entry for each supported data rate.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
> ---
> changes in v3:-
> - Update the description to specfify about entries of the array (rob)
> changes in v2:-
> - Split N_FTS & L1 and L0s entry delay in two patches (bjorn)
> - Update the commit text, description (bjorn)
> 
> Krishna Chaitanya Chundru (2):
>   schemas: pci: bridge: Document PCI L0s & L1 entry delay
>   schemas: pci: bridge: Document PCIe N_FTS
> 
>  dtschema/schemas/pci/pci-bus-common.yaml | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Applied, thanks.

Rob