linux-kernel - Re: [PATCH v9 1/4] clocksource: mips-gic-timer: Enable counter when CPUs start

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Message-ID: <Z7XFnshoa_VS91HN@alpha.franken.de>
Date: Wed, 19 Feb 2025 12:50:54 +0100
From: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To: daniel.lezcano@...aro.org
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Gregory CLEMENT <gregory.clement@...tlin.com>,
	Serge Semin <fancer.lancer@...il.com>,
	Jiaxun Yang <jiaxun.yang@...goat.com>,
	Paul Burton <paulburton@...nel.org>, Chao-ying Fu <cfu@...s.com>,
	Djordje Todorovic <djordje.todorovic@...cgroup.com>,
	Aleksandar Rikalo <arikalo@...il.com>
Subject: Re: [PATCH v9 1/4] clocksource: mips-gic-timer: Enable counter when
 CPUs start

On Wed, Jan 29, 2025 at 01:32:47PM +0100, Aleksandar Rikalo wrote:
> From: Paul Burton <paulburton@...nel.org>
> 
> In multi-cluster MIPS I6500 systems there is a GIC in each cluster,
> each with its own counter. When a cluster powers up the counter will
> be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register.
> 
> In single cluster systems, it has been fine to clear COUNTSTOP once
> in gic_clocksource_of_init() to start the counter. In multi-cluster
> systems, this will only have started the counter in the boot cluster,
> and any CPUs in other clusters will find their counter stopped which
> will break the GIC clock_event_device.
> 
> Resolve this by having CPUs clear the COUNTSTOP bit when they come
> online, using the existing gic_starting_cpu() CPU hotplug callback. This
> will allow CPUs in secondary clusters to ensure that the cluster's GIC
> counter is running as expected.
> 
> Signed-off-by: Paul Burton <paulburton@...nel.org>
> Signed-off-by: Chao-ying Fu <cfu@...ecomp.com>
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@...mia.com>
> Signed-off-by: Aleksandar Rikalo <arikalo@...il.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@...aro.org>
> Tested-by: Serge Semin <fancer.lancer@...il.com>
> Tested-by: Gregory CLEMENT <gregory.clement@...tlin.com>
> ---
>  drivers/clocksource/mips-gic-timer.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
> index 7907b740497a..abb685a080a5 100644
> --- a/drivers/clocksource/mips-gic-timer.c
> +++ b/drivers/clocksource/mips-gic-timer.c
> @@ -115,6 +115,9 @@ static void gic_update_frequency(void *data)
>  
>  static int gic_starting_cpu(unsigned int cpu)
>  {
> +	/* Ensure the GIC counter is running */
> +	clear_gic_config(GIC_CONFIG_COUNTSTOP);
> +
>  	gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
>  	return 0;
>  }
> @@ -288,9 +291,6 @@ static int __init gic_clocksource_of_init(struct device_node *node)
>  			pr_warn("Unable to register clock notifier\n");
>  	}
>  
> -	/* And finally start the counter */
> -	clear_gic_config(GIC_CONFIG_COUNTSTOP);
> -
>  	/*
>  	 * It's safe to use the MIPS GIC timer as a sched clock source only if
>  	 * its ticks are stable, which is true on either the platforms with
> -- 
> 2.25.1

Daniel are you ok to take this patch trough the mips tree ? If yes,
could I get an ack for it ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]