lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <c65a86a5-fc65-4144-b780-ed9e8a59f1ab@linaro.org>
Date: Wed, 19 Feb 2025 13:38:45 +0100
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: Aleksandar Rikalo <arikalo@...il.com>, linux-mips@...r.kernel.org
Cc: linux-kernel@...r.kernel.org,
 Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
 Thomas Gleixner <tglx@...utronix.de>,
 Gregory CLEMENT <gregory.clement@...tlin.com>,
 Serge Semin <fancer.lancer@...il.com>, Jiaxun Yang
 <jiaxun.yang@...goat.com>, Paul Burton <paulburton@...nel.org>,
 Chao-ying Fu <cfu@...s.com>,
 Djordje Todorovic <djordje.todorovic@...cgroup.com>
Subject: Re: [PATCH v9 1/4] clocksource: mips-gic-timer: Enable counter when
 CPUs start

On 29/01/2025 13:32, Aleksandar Rikalo wrote:
> From: Paul Burton <paulburton@...nel.org>
> 
> In multi-cluster MIPS I6500 systems there is a GIC in each cluster,
> each with its own counter. When a cluster powers up the counter will
> be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register.
> 
> In single cluster systems, it has been fine to clear COUNTSTOP once
> in gic_clocksource_of_init() to start the counter. In multi-cluster
> systems, this will only have started the counter in the boot cluster,
> and any CPUs in other clusters will find their counter stopped which
> will break the GIC clock_event_device.
> 
> Resolve this by having CPUs clear the COUNTSTOP bit when they come
> online, using the existing gic_starting_cpu() CPU hotplug callback. This
> will allow CPUs in secondary clusters to ensure that the cluster's GIC
> counter is running as expected.
> 
> Signed-off-by: Paul Burton <paulburton@...nel.org>
> Signed-off-by: Chao-ying Fu <cfu@...ecomp.com>
> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@...mia.com>
> Signed-off-by: Aleksandar Rikalo <arikalo@...il.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@...aro.org>
> Tested-by: Serge Semin <fancer.lancer@...il.com>
> Tested-by: Gregory CLEMENT <gregory.clement@...tlin.com>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@...aro.org>


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ