linux-kernel - Re: [PATCH 2/7] drm/msm/dpu: program master INTF value

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Message-ID: <btkhximqopd3wmp7hxape6hsx53kzdfyl5ciyu5fe472nphzra@lbq3ybphm4h3>
Date: Fri, 21 Feb 2025 00:20:41 +0100
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Rob Clark <robdclark@...il.com>, 
	Abhinav Kumar <quic_abhinavk@...cinc.com>, Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>, 
	Simona Vetter <simona@...ll.ch>, linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, 
	freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/7] drm/msm/dpu: program master INTF value

On 2025-02-20 12:26:19, Dmitry Baryshkov wrote:
> If several interfaces are being handled through a single CTL, a main
> ('master') INTF needs to be programmed into a separate register. Write
> corresponding value into that register.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 321a89e6400d2824ebda2c08be5e6943cb0f6b11..db36bfa98fc310c1bf35c4817d601ae6cf88d151 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -582,6 +582,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>  	DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
>  	DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
>  
> +	if (cfg->intf_master)
> +		DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0));
> +

We should not forget to unset the master mode when this INTF is "removed"
from the CTL.  When I modified and prepared your patches for sending, I did
it like this to only clear it in reset_intf_v1 if the current intf is equal to
the mater interface, similar to how it's removing the current intf _bit_ from
CTL_INTF_ACTIVE without touching the rest:

https://github.com/SoMainline/linux/commit/f5a0789c3b9fcba08f6e8fb67637d16dc553cb9b#diff-e9e5209e670102755be2a30d223e79da644dfb8c28ac2ef61e5c49bb46457bb9R667-R673

>  	if (cfg->merge_3d)
>  		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 85c6c835cc8780e6cb66f3a262d9897c91962935..e95989a2fdda6344d0cb9d3036e6ed22a0458675 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg {
>  /**
>   * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
>   * @intf :                 Interface id
> + * @intf_master:           Master interface id in the dual pipe topology

Will this apply to quad topology etc as well?  Maybe needs to be generalized.

- Marijn

>   * @mode_3d:               3d mux configuration
>   * @merge_3d:              3d merge block used
>   * @intf_mode_sel:         Interface mode, cmd / vid
> @@ -45,6 +46,7 @@ struct dpu_hw_stage_cfg {
>   */
>  struct dpu_hw_intf_cfg {
>  	enum dpu_intf intf;
> +	enum dpu_intf intf_master;
>  	enum dpu_wb wb;
>  	enum dpu_3d_blend_mode mode_3d;
>  	enum dpu_merge_3d merge_3d;
> 
> -- 
> 2.39.5
>