linux-kernel - Re: [PATCH bpf-next v3 6/9] arm64: insn: Add load-acquire and store-release instructions

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Message-ID: <CAADnVQ+bJwwYKCU-HRWdgdfpc4pETxsVFtBOKAvfzLrR0Xvs4A@mail.gmail.com>
Date: Fri, 21 Feb 2025 19:11:32 -0800
From: Alexei Starovoitov <alexei.starovoitov@...il.com>
To: Peilin Ye <yepeilin@...gle.com>
Cc: bpf <bpf@...r.kernel.org>, 
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, bpf@...f.org, 
	Xu Kuohai <xukuohai@...weicloud.com>, Eduard Zingerman <eddyz87@...il.com>, 
	David Vernet <void@...ifault.com>, Alexei Starovoitov <ast@...nel.org>, 
	Daniel Borkmann <daniel@...earbox.net>, Andrii Nakryiko <andrii@...nel.org>, 
	Martin KaFai Lau <martin.lau@...ux.dev>, Song Liu <song@...nel.org>, 
	Yonghong Song <yonghong.song@...ux.dev>, John Fastabend <john.fastabend@...il.com>, 
	KP Singh <kpsingh@...nel.org>, Stanislav Fomichev <sdf@...ichev.me>, Hao Luo <haoluo@...gle.com>, 
	Jiri Olsa <jolsa@...nel.org>, Jonathan Corbet <corbet@....net>, 
	"Paul E. McKenney" <paulmck@...nel.org>, Puranjay Mohan <puranjay@...nel.org>, 
	Ilya Leoshkevich <iii@...ux.ibm.com>, Heiko Carstens <hca@...ux.ibm.com>, Vasily Gorbik <gor@...ux.ibm.com>, 
	Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, 
	Quentin Monnet <qmo@...nel.org>, Mykola Lysenko <mykolal@...com>, Shuah Khan <shuah@...nel.org>, 
	Ihor Solodrai <ihor.solodrai@...ux.dev>, Yingchi Long <longyingchi24s@....ac.cn>, 
	Josh Don <joshdon@...gle.com>, Barret Rhoden <brho@...gle.com>, Neel Natu <neelnatu@...gle.com>, 
	Benjamin Segall <bsegall@...gle.com>, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH bpf-next v3 6/9] arm64: insn: Add load-acquire and
 store-release instructions

On Wed, Feb 19, 2025 at 5:21 PM Peilin Ye <yepeilin@...gle.com> wrote:
>
> Add load-acquire ("load_acq", LDAR{,B,H}) and store-release
> ("store_rel", STLR{,B,H}) instructions.  Breakdown of encoding:
>
>                                 size        L   (Rs)  o0 (Rt2) Rn    Rt
>              mask (0x3fdffc00): 00 111111 1 1 0 11111 1  11111 00000 00000
>   value, load_acq (0x08dffc00): 00 001000 1 1 0 11111 1  11111 00000 00000
>  value, store_rel (0x089ffc00): 00 001000 1 0 0 11111 1  11111 00000 00000
>
> As suggested by Xu [1], include all Should-Be-One (SBO) bits ("Rs" and
> "Rt2" fields) in the "mask" and "value" numbers.
>
> It is worth noting that we are adding the "no offset" variant of STLR
> instead of the "pre-index" variant, which has a different encoding.
>
> Reference: Arm Architecture Reference Manual (ARM DDI 0487K.a,
>            ID032224),
>
>   * C6.2.161 LDAR
>   * C6.2.353 STLR
>
> [1] https://lore.kernel.org/bpf/4e6641ce-3f1e-4251-8daf-4dd4b77d08c4@huaweicloud.com/
>
> Signed-off-by: Peilin Ye <yepeilin@...gle.com>
> ---
>  arch/arm64/include/asm/insn.h |  8 ++++++++
>  arch/arm64/lib/insn.c         | 29 +++++++++++++++++++++++++++++
>  2 files changed, 37 insertions(+)
>
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index 2d8316b3abaf..39577f1d079a 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -188,8 +188,10 @@ enum aarch64_insn_ldst_type {
>         AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
>         AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
>         AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
> +       AARCH64_INSN_LDST_LOAD_ACQ,
>         AARCH64_INSN_LDST_LOAD_EX,
>         AARCH64_INSN_LDST_LOAD_ACQ_EX,
> +       AARCH64_INSN_LDST_STORE_REL,
>         AARCH64_INSN_LDST_STORE_EX,
>         AARCH64_INSN_LDST_STORE_REL_EX,
>         AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET,

Xu, Puranjay, other arm experts,

Please help review these patches.

Thanks!