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Message-ID: <7853efad-6158-420e-aba6-65afbcbaea79@huaweicloud.com>
Date: Sat, 22 Feb 2025 17:27:09 +0800
From: Xu Kuohai <xukuohai@...weicloud.com>
To: Peilin Ye <yepeilin@...gle.com>, bpf@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Cc: bpf@...f.org, Eduard Zingerman <eddyz87@...il.com>,
David Vernet <void@...ifault.com>, Alexei Starovoitov <ast@...nel.org>,
Daniel Borkmann <daniel@...earbox.net>, Andrii Nakryiko <andrii@...nel.org>,
Martin KaFai Lau <martin.lau@...ux.dev>, Song Liu <song@...nel.org>,
Yonghong Song <yonghong.song@...ux.dev>,
John Fastabend <john.fastabend@...il.com>, KP Singh <kpsingh@...nel.org>,
Stanislav Fomichev <sdf@...ichev.me>, Hao Luo <haoluo@...gle.com>,
Jiri Olsa <jolsa@...nel.org>, Jonathan Corbet <corbet@....net>,
"Paul E. McKenney" <paulmck@...nel.org>, Puranjay Mohan
<puranjay@...nel.org>, Ilya Leoshkevich <iii@...ux.ibm.com>,
Heiko Carstens <hca@...ux.ibm.com>, Vasily Gorbik <gor@...ux.ibm.com>,
Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
Quentin Monnet <qmo@...nel.org>, Mykola Lysenko <mykolal@...com>,
Shuah Khan <shuah@...nel.org>, Ihor Solodrai <ihor.solodrai@...ux.dev>,
Yingchi Long <longyingchi24s@....ac.cn>, Josh Don <joshdon@...gle.com>,
Barret Rhoden <brho@...gle.com>, Neel Natu <neelnatu@...gle.com>,
Benjamin Segall <bsegall@...gle.com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH bpf-next v3 6/9] arm64: insn: Add load-acquire and
store-release instructions
On 2/20/2025 9:21 AM, Peilin Ye wrote:
> Add load-acquire ("load_acq", LDAR{,B,H}) and store-release
> ("store_rel", STLR{,B,H}) instructions. Breakdown of encoding:
>
> size L (Rs) o0 (Rt2) Rn Rt
> mask (0x3fdffc00): 00 111111 1 1 0 11111 1 11111 00000 00000
> value, load_acq (0x08dffc00): 00 001000 1 1 0 11111 1 11111 00000 00000
> value, store_rel (0x089ffc00): 00 001000 1 0 0 11111 1 11111 00000 00000
>
> As suggested by Xu [1], include all Should-Be-One (SBO) bits ("Rs" and
> "Rt2" fields) in the "mask" and "value" numbers.
>
> It is worth noting that we are adding the "no offset" variant of STLR
> instead of the "pre-index" variant, which has a different encoding.
>
> Reference: Arm Architecture Reference Manual (ARM DDI 0487K.a,
> ID032224),
>
> * C6.2.161 LDAR
> * C6.2.353 STLR
>
> [1] https://lore.kernel.org/bpf/4e6641ce-3f1e-4251-8daf-4dd4b77d08c4@huaweicloud.com/
>
> Signed-off-by: Peilin Ye <yepeilin@...gle.com>
> ---
> arch/arm64/include/asm/insn.h | 8 ++++++++
> arch/arm64/lib/insn.c | 29 +++++++++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index 2d8316b3abaf..39577f1d079a 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -188,8 +188,10 @@ enum aarch64_insn_ldst_type {
> AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
> AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
> AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
> + AARCH64_INSN_LDST_LOAD_ACQ,
> AARCH64_INSN_LDST_LOAD_EX,
> AARCH64_INSN_LDST_LOAD_ACQ_EX,
> + AARCH64_INSN_LDST_STORE_REL,
> AARCH64_INSN_LDST_STORE_EX,
> AARCH64_INSN_LDST_STORE_REL_EX,
> AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET,
> @@ -351,6 +353,8 @@ __AARCH64_INSN_FUNCS(ldr_imm, 0x3FC00000, 0x39400000)
> __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
> __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
> __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
> +__AARCH64_INSN_FUNCS(load_acq, 0x3FDFFC00, 0x08DFFC00)
> +__AARCH64_INSN_FUNCS(store_rel, 0x3FDFFC00, 0x089FFC00)
> __AARCH64_INSN_FUNCS(load_ex, 0x3FC00000, 0x08400000)
> __AARCH64_INSN_FUNCS(store_ex, 0x3FC00000, 0x08000000)
> __AARCH64_INSN_FUNCS(mops, 0x3B200C00, 0x19000400)
> @@ -602,6 +606,10 @@ u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
> int offset,
> enum aarch64_insn_variant variant,
> enum aarch64_insn_ldst_type type);
> +u32 aarch64_insn_gen_load_acq_store_rel(enum aarch64_insn_register reg,
> + enum aarch64_insn_register base,
> + enum aarch64_insn_size_type size,
> + enum aarch64_insn_ldst_type type);
> u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
> enum aarch64_insn_register base,
> enum aarch64_insn_register state,
> diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
> index b008a9b46a7f..9bef696e2230 100644
> --- a/arch/arm64/lib/insn.c
> +++ b/arch/arm64/lib/insn.c
> @@ -540,6 +540,35 @@ u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
> offset >> shift);
> }
>
> +u32 aarch64_insn_gen_load_acq_store_rel(enum aarch64_insn_register reg,
> + enum aarch64_insn_register base,
> + enum aarch64_insn_size_type size,
> + enum aarch64_insn_ldst_type type)
> +{
> + u32 insn;
> +
> + switch (type) {
> + case AARCH64_INSN_LDST_LOAD_ACQ:
> + insn = aarch64_insn_get_load_acq_value();
> + break;
> + case AARCH64_INSN_LDST_STORE_REL:
> + insn = aarch64_insn_get_store_rel_value();
> + break;
> + default:
> + pr_err("%s: unknown load-acquire/store-release encoding %d\n",
> + __func__, type);
> + return AARCH64_BREAK_FAULT;
> + }
> +
> + insn = aarch64_insn_encode_ldst_size(size, insn);
> +
> + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
> + reg);
> +
> + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
> + base);
> +}
> +
> u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
> enum aarch64_insn_register base,
> enum aarch64_insn_register state,
Looks good to me
Acked-by: Xu Kuohai <xukuohai@...wei.com>
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