[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20250222-fml13v01_emmc_speed-v2-2-3ffc5b1f5663@hotmail.com>
Date: Sat, 22 Feb 2025 14:34:16 +0100
From: Maud Spierings via B4 Relay <devnull+maud_spierings.hotmail.com@...nel.org>
To: Conor Dooley <conor@...nel.org>, Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Maud Spierings <maud_spierings@...mail.com>
Subject: [PATCH v2 2/2] riscv: dts: starfive: fml13v01: increase eMMC bus
speed
From: Maud Spierings <maud_spierings@...mail.com>
The assigned clock speed of 50 MHz is limitting this interface which is
SDIO 5.0 capable. Sadly at 200MHz it fails to mount an eMMC drive,
150MHz (really 132 MHz) is the highest it was able to get.
This improves the seq read/write performance by 2x~
Signed-off-by: Maud Spierings <maud_spierings@...mail.com>
---
arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index 8d9ce8b69a71be78ca57618ae842c9f415648450..63b539bedd63d39dbe2096f85aaf70ba6ab64d29 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -11,6 +11,10 @@ / {
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
};
+&mmc0 {
+ assigned-clock-rates = <150000000>;
+};
+
&pcie1 {
perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
--
2.48.1
Powered by blists - more mailing lists