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Message-Id: <174040575668.71176.5895162308675381424.b4-ty@collabora.com>
Date: Mon, 24 Feb 2025 15:02:36 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Chun-Kuang Hu <chunkuang.hu@...nel.org>, 
 Jason-JH Lin <jason-jh.lin@...iatek.com>
Cc: Nancy Lin <nancy.lin@...iatek.com>, 
 Singo Chang <singo.chang@...iatek.com>, 
 Yongqiang Niu <yongqiang.niu@...iatek.com>, 
 Sirius Wang <sirius.wang@...iatek.com>, 
 Xavier Chang <xavier.chang@...iatek.com>, Fei Shao <fshao@...omium.org>, 
 Chen-yu Tsai <wenst@...omium.org>, Pin-yen Lin <treapking@...omium.org>, 
 dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org, 
 linux-mediatek@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, 
 Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v2] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting

On Mon, 24 Feb 2025 18:50:13 +0800, Jason-JH Lin wrote:
> Add cmdq_gctl_value_toggle() to configure GCE_CTRL_BY_SW and GCE_DDR_EN
> together in the same GCE_GCTL_VALUE register.
> 
> For the SoCs whose GCE is located in MMINFRA and uses MMINFRA_AO power,
> this allows it to be written without enabling the clocks. Otherwise, all
> GCE registers should be written after the GCE clocks are enabled.
> Move this function into cmdq_runtime_resume() and cmdq_runtime_suspend()
> to ensure it is called when the GCE clock is enabled.
> 
> [...]

Applied to v6.14-next/soc, thanks!

[1/1] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting
      commit: 6b9a5fc65a7880f7ac6a981a0a30b5ecba7bd5ae

Cheers,
Angelo



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