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Message-ID: <7af26747-34cd-4088-a6b5-865de9e87fba@collabora.com>
Date: Thu, 6 Mar 2025 11:53:53 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Jason-JH Lin <jason-jh.lin@...iatek.com>,
 Chun-Kuang Hu <chunkuang.hu@...nel.org>
Cc: Nancy Lin <nancy.lin@...iatek.com>, Singo Chang
 <singo.chang@...iatek.com>, Yongqiang Niu <yongqiang.niu@...iatek.com>,
 Sirius Wang <sirius.wang@...iatek.com>,
 Xavier Chang <xavier.chang@...iatek.com>, Fei Shao <fshao@...omium.org>,
 Chen-yu Tsai <wenst@...omium.org>, Pin-yen Lin <treapking@...omium.org>,
 dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
 linux-mediatek@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org,
 Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v2] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting

Il 24/02/25 11:50, Jason-JH Lin ha scritto:
> Add cmdq_gctl_value_toggle() to configure GCE_CTRL_BY_SW and GCE_DDR_EN
> together in the same GCE_GCTL_VALUE register.
> 
> For the SoCs whose GCE is located in MMINFRA and uses MMINFRA_AO power,
> this allows it to be written without enabling the clocks. Otherwise, all
> GCE registers should be written after the GCE clocks are enabled.
> Move this function into cmdq_runtime_resume() and cmdq_runtime_suspend()
> to ensure it is called when the GCE clock is enabled.
> 
> Fixes: 7abd037aa581 ("mailbox: mtk-cmdq: add gce ddr enable support flow")
> Signed-off-by: Jason-JH Lin <jason-jh.lin@...iatek.com>

I have erroneously picked this patch in the MediaTek tree, as I had misread the
changed file, thought that it was mtk-cmdq-helper.c.

This patch also has the wrong recipients, as this should not go through the
MediaTek trees, but through the mailbox one.

Therefore, I dropped this patch from the MediaTek tree - sorry for the confusion.

Regards,
Angelo

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