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Message-ID: <20250224180150.3689638-9-fabrice.gasnier@foss.st.com>
Date: Mon, 24 Feb 2025 19:01:50 +0100
From: Fabrice Gasnier <fabrice.gasnier@...s.st.com>
To: <lee@...nel.org>, <ukleinek@...nel.org>, <alexandre.torgue@...s.st.com>,
<robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<wbg@...nel.org>, <jic23@...nel.org>, <daniel.lezcano@...aro.org>,
<tglx@...utronix.de>
CC: <catalin.marinas@....com>, <will@...nel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<linux-iio@...r.kernel.org>, <linux-pwm@...r.kernel.org>,
<olivier.moysan@...s.st.com>, <fabrice.gasnier@...s.st.com>
Subject: [PATCH 8/8] arm64: dts: st: add low-power timer nodes on stm32mp251
Add low-power timer (LPTimer) support on STM32MP25 SoC.
The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a
smaller set of features (no capture/compare) channel. Still, LPTIM5 can
be used as single PWM, counter, trigger or timer.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@...s.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 177 +++++++++++++++++++++++++
1 file changed, 177 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index f3c6cdfd7008..742367e4f16d 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -238,6 +238,78 @@ rifsc: bus@...80000 {
#access-controller-cells = <1>;
ranges;
+ lptimer1: timer@...90000 {
+ compatible = "st,stm32mp25-lptimer";
+ reg = <0x40090000 0x400>;
+ interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM1>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 17>;
+ power-domains = <&RET_PD>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@0 {
+ compatible = "st,stm32mp25-lptimer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+ };
+
+ lptimer2: timer@...a0000 {
+ compatible = "st,stm32mp25-lptimer";
+ reg = <0x400a0000 0x400>;
+ interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM2>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 18>;
+ power-domains = <&RET_PD>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@1 {
+ compatible = "st,stm32mp25-lptimer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+
i2s2: audio-controller@...b0000 {
compatible = "st,stm32mp25-i2s";
reg = <0x400b0000 0x400>;
@@ -799,6 +871,111 @@ i2c8: i2c@...40000 {
status = "disabled";
};
+ lptimer3: timer@...50000 {
+ compatible = "st,stm32mp25-lptimer";
+ reg = <0x46050000 0x400>;
+ interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM3>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 19>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@2 {
+ compatible = "st,stm32mp25-lptimer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ lptimer4: timer@...60000 {
+ compatible = "st,stm32mp25-lptimer";
+ reg = <0x46060000 0x400>;
+ interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM4>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 20>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@3 {
+ compatible = "st,stm32mp25-lptimer-trigger";
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
+ lptimer5: timer@...70000 {
+ compatible = "st,stm32mp25-lptimer";
+ reg = <0x46070000 0x400>;
+ interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_LPTIM5>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&rifsc 21>;
+ wakeup-source;
+ status = "disabled";
+
+ counter {
+ compatible = "st,stm32mp25-lptimer-counter";
+ status = "disabled";
+ };
+
+ pwm {
+ compatible = "st,stm32mp25-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer {
+ compatible = "st,stm32mp25-lptimer-timer";
+ status = "disabled";
+ };
+
+ trigger@4 {
+ compatible = "st,stm32mp25-lptimer-trigger";
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+
csi: csi@...20000 {
compatible = "st,stm32mp25-csi";
reg = <0x48020000 0x2000>;
--
2.25.1
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