linux-kernel - Re: (subset) [PATCH v2 0/6] X1P42100 DT and PCIe PHY bits

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Message-ID: <174057724682.237840.3212969107242689758.b4-ty@kernel.org>
Date: Wed, 26 Feb 2025 07:40:45 -0600
From: Bjorn Andersson <andersson@...nel.org>
To: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
	linux-arm-msm@...r.kernel.org,
	linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
	Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
	Jens Glathe <jens.glathe@...schoolsolutions.biz>
Subject: Re: (subset) [PATCH v2 0/6] X1P42100 DT and PCIe PHY bits


On Mon, 03 Feb 2025 15:43:19 +0100, Konrad Dybcio wrote:
> X1P42100 is a(n indirect) derivative of X1E80100 - the silicon is
> actually different and it's not a fused down part.
> 
> Introduce the DTS bits required to support it by mostly reusing the
> X1E SoC and CRD DTSIs. The most notable differences from our software
> PoV are a different GPU (support for which will be added later), 4
> less CPUs and some nuances in the PCIe hardware.
> 
> [...]

Applied, thanks!

[4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets
      commit: 62ca6669d62eb554eb467f2953cabb4238e18823
[5/6] arm64: dts: qcom: Commonize X1 CRD DTSI
      commit: fbf5e007588f3f2bace84309b4a0d428ad619322
[6/6] arm64: dts: qcom: Add X1P42100 SoC and CRD
      commit: f08edb5299166b7c6d4eae439b1d3f81c31ba50e

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>