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Message-Id: <20250226-irqchip-gpio-a4-a5-v2-2-c55b1050cb55@amlogic.com>
Date: Wed, 26 Feb 2025 13:47:53 +0800
From: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@...nel.org>
To: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Kevin Hilman <khilman@...libre.com>, Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Heiner Kallweit <hkallweit1@...il.com>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org,
Xianwei Zhao <xianwei.zhao@...ogic.com>
Subject: [PATCH v2 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs
From: Xianwei Zhao <xianwei.zhao@...ogic.com>
The Amlogic A4 SoCs support 12 GPIO IRQ lines and 2 AO GPIO IRQ lines,
A5 SoCs support 12 GPIO IRQ lines, details are as below.
A4 IRQ Number:
- 72:55 18 pins on bank T
- 54:32 23 pins on bank X
- 31:16 16 pins on bank D
- 15:14 2 pins on bank E
- 13:0 14 pins on bank B
A4 AO IRQ Number:
- 7 1 pin on bank TESTN
- 6:0 7 pins on bank AO
A5 IRQ Number:
- 98 1 pin on bank TESTN
- 97:82 16 pins on bank Z
- 81:62 20 pins on bank X
- 61:48 14 pins on bank T
- 47:32 16 pins on bank D
- 31:27 5 pins on bank H
- 26:25 2 pins on bank E
- 24:14 11 pins on bank C
- 13:0 14 pins on bank B
Signed-off-by: Xianwei Zhao <xianwei.zhao@...ogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 42 +++++++++++++++++++++++++++++++++++-----
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index cd789fa51519..f1cf0c228ca4 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -26,8 +26,6 @@
/* use for A1 like chips */
#define REG_PIN_A1_SEL 0x04
-/* Used for s4 chips */
-#define REG_EDGE_POL_S4 0x1c
/*
* Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
@@ -57,6 +55,8 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
unsigned int type, u32 *channel_hwirq);
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int type, u32 *channel_hwirq);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -72,6 +72,7 @@ struct meson_gpio_irq_params {
bool support_edge_both;
unsigned int edge_both_offset;
unsigned int edge_single_offset;
+ unsigned int edge_pol_reg;
unsigned int pol_low_offset;
unsigned int pin_sel_mask;
struct irq_ctl_ops ops;
@@ -105,6 +106,18 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_A4_AO_COMMON_DATA(irqs) \
+ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
+ meson_a1_gpio_irq_sel_pin, \
+ meson_s4_gpio_irq_set_type) \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .edge_pol_reg = 0x8, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 2, \
+
#define INIT_MESON_S4_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
meson_a1_gpio_irq_sel_pin, \
@@ -112,6 +125,7 @@ struct meson_gpio_irq_params {
.support_edge_both = true, \
.edge_both_offset = 0, \
.edge_single_offset = 12, \
+ .edge_pol_reg = 0x1c, \
.pol_low_offset = 0, \
.pin_sel_mask = 0xff, \
.nr_channels = 12, \
@@ -146,6 +160,18 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params a4_params = {
+ INIT_MESON_S4_COMMON_DATA(81)
+};
+
+static const struct meson_gpio_irq_params a4_ao_params = {
+ INIT_MESON_A4_AO_COMMON_DATA(8)
+};
+
+static const struct meson_gpio_irq_params a5_params = {
+ INIT_MESON_S4_COMMON_DATA(99)
+};
+
static const struct meson_gpio_irq_params s4_params = {
INIT_MESON_S4_COMMON_DATA(82)
};
@@ -168,6 +194,9 @@ static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
+ { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
+ { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
+ { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
{ }
@@ -358,16 +387,19 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
{
u32 val = 0;
unsigned int idx;
+ const struct meson_gpio_irq_params *params;
+
+ params = ctl->params;
idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
type &= IRQ_TYPE_SENSE_MASK;
- meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
+ meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0);
if (type == IRQ_TYPE_EDGE_BOTH) {
val |= BIT(ctl->params->edge_both_offset + idx);
- meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
+ meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,
BIT(ctl->params->edge_both_offset + idx), val);
return 0;
}
@@ -378,7 +410,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
val |= BIT(ctl->params->edge_single_offset + idx);
- meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,
BIT(idx) | BIT(12 + idx), val);
return 0;
};
--
2.37.1
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