Message-ID: <627fdd72-4383-4172-9a51-c77ea32b7c60@quicinc.com>
Date: Wed, 26 Feb 2025 15:05:13 +0800
From: Jie Gan <quic_jiegan@...cinc.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
        Mike Leach
	<mike.leach@...aro.org>,
        James Clark <james.clark@...aro.org>,
        "Alexander
 Shishkin" <alexander.shishkin@...ux.intel.com>,
        Maxime Coquelin
	<mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
CC: Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Jinlong Mao
	<quic_jinlmao@...cinc.com>, <coresight@...ts.linaro.org>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [PATCH v14 00/10] Coresight: Add Coresight TMC Control Unit
 driver



On 2/26/2025 12:13 PM, Jie Gan wrote:
> The Coresight TMC Control Unit(CTCU) device hosts miscellaneous configuration
> registers to control various features related to TMC ETR device.
> 

[...]
Hi, James

Sorry for the mistake, I just found I forget to add the co-developed-by 
tag to patch(5/10), patch(6/10) after the division.

Do I need resend the patch series?

Jie

> 
> Sincere thanks to James Clark for providing an excellent idea to handle
> the trace_id of the path.
> 
> ---
> Changes in V14:
> 1. Drop the reviewed-by tag for previous patch: Coresight-Introduce-a-new-struct-coresight_path
>     due to a massive modification.
> 2. Split the patch, Coresight-Introduce-a-new-struct-coresight_path, into
>     four patches.
>     - Coresight-Introduce-a-new-struct-coresight_path
>     - Coresight-Allocate-trace-ID-after-building-the-path
>     - Coresight-Change-to-read-the-trace-ID-from-coresight_path
>     - Coresight-Change-functions-to-accept-the-coresight_path
> 3. Change the type of the coresight_path_assign_trace_id function to void.
> 4. Change the type of the path_list from struct list_head * to struct list_head to avoid
>     extra memory allocate/free.
> 5. Rename the file coresight-ctcu.c to coresight-ctcu-core.c to improve scalibility.
> 6. Add pm_ops for CTCU driver.
> 7. Rename the struct ctcu_atid_config to ctcu_etr_config to improve scalibility.
> 8. Optimize following functions of the CTCU driver to improve readability.
>     - ctcu_program_atid_register
>     - __ctcu_set_etr_traceid
> 9. Change the way to get the port number. The new solution is searching
>     the sink device from CTCU's view.
> 10. Add desc.access for CTCU driver.
> Link to V13 - https://lore.kernel.org/linux-arm-msm/20250221060543.2898845-1-quic_jiegan@quicinc.com/
> ---
> 
> ---
> Changes in V13:
> 1. Move the trace_id callback to coresight_ops to simplify the code.
> Link to V12 - https://lore.kernel.org/linux-arm-msm/20250217093024.1133096-1-quic_jiegan@quicinc.com/
> ---
> 
> ---
> Changes in V12:
> 1. Update the method for allocating trace_id for perf mode.
> Link to V11 - https://lore.kernel.org/linux-arm-msm/20250214024021.249655-1-quic_jiegan@quicinc.com/
> ---
> 
> ---
> Changes in V11:
> 1. Add reviewed-by tag to patch(2/7), (4/7), (6/7). Patch(3/7) is
>     contributed by James, so didnot add reviewed-by tag of James.
> 2. Fix warning reported by kernel bot and verified with build(W=1).
> 3. Restore to the original logic that responsible for allocate trace_id
>     of ETM device in perf mode according to James' comment.
> Link to V10 - https://lore.kernel.org/linux-arm-msm/20250207064213.2314482-1-quic_jiegan@quicinc.com/
> ---
> 
> ---
> Changes in V10:
> 1. Introduce a new API to allocate and read trace_id after path is built.
> 2. Introduce a new API to allocate and read trace_id of ETM device.
> 3. Add a new patch: [PATCH v10 3/7] Coresight: Use coresight_etm_get_trace_id() in traceid_show()
> 4. Remove perf handle from coresight_path.
> 5. Use u8 instead of atomic_t for traceid_refcnt.
> 6. Optimize the part of code in CTCU drvier that is responsible for program atid register.
> Link to V9 - https://lore.kernel.org/all/20250124072537.1801030-1-quic_jiegan@quicinc.com/
> 
> Changes in V9:
> 1. Rebased on tag next-20250113.
> 2. Separate the previous trace_id patch (patch 2/5 Coresight: Add trace_id function to
>     retrieving the trace ID) into two patches.
> 3. Introduce a new struct coresight_path instead of cs_sink_data which was
>     created in previous version. The coresight_path will be initialized
>     and constructed in coresight_build_path function and released by
>     coresight_release_path function.
>     Detail of the struct coresight_path is shown below:
> /**
>   * struct coresight_path - data needed by enable/disable path
>   * @path:               path from source to sink.
>   * @trace_id:           trace_id of the whole path.
>   */
> struct coresight_path {
>          struct list_head                *path;
>          u8                              trace_id;
> };
> 
> 4. Introduce an array of atomic in CTCU driver to represent the refcnt or each
>     enabled trace_id for each sink. The reason is there is a scenario that more
>     than one TPDM device physically connected to the same TPDA device has
>     been enabled. The CTCU driver must verify the refcnt before resetting the
>     bit of the atid register according to the trace_id of the TPDA device.
> 5. Remove redundant codes in CTCU driver.
> 6. Add reviewed-by tag to the commit message for APB clock path(patch
>     1/5).
> Link to V8 - https://lore.kernel.org/all/20241226011022.1477160-1-quic_jiegan@quicinc.com/
> 
> Changes in V8:
> 1. Rebased on tag next-20241220.
> 2. Use raw_spinlock_t instead of spinlock_t.
> 3. Remove redundant codes in CTCU driver:
>     - Eliminate unnecessary parameter validations.
>     - Correct log level when an error occurs.
>     - Optimize codes.
> 4. Correct the subject prefix for DT patch.
> 5. Collected reviewed-by tag from Konrad Dybcib for DT patch.
> Link to V7 - https://lore.kernel.org/all/20241210031545.3468561-1-quic_jiegan@quicinc.com/
> 
> Changes in V7:
> 1. Rebased on tag next-20241204.
> 2. Fix format issue for dts patch.
>     - Padding the address part to 8 digits
> Link to V6 - https://lore.kernel.org/linux-arm-msm/20241009112503.1851585-1-quic_jiegan@quicinc.com/
> 
> Changes in V6:
> 1. Collected reviewed-by tag from Rob for dt-binding patch.
> 2. Rebased on tag next-20241008.
> 3. Dropped all depends-on tags.
> Link to V5 - https://lore.kernel.org/linux-arm-msm/20240909033458.3118238-1-quic_jiegan@quicinc.com/
> 
> Changes in V5:
> 1. Fix the format issue for description paragrah in dt binding file.
> 2. Previous discussion for why use "in-ports" property instead of "ports".
> Link to V4 - https://lore.kernel.org/linux-arm-msm/20240828012706.543605-1-quic_jiegan@quicinc.com/
> 
> Changes in V4:
> 1. Add TMC description in binding file.
> 2. Restrict the number of ports for the CTCU device to a range of 0 to 1 in the binding file,
>     because the maximum number of CTCU devices is 2 for existing projects.
> Link to V3 - https://lore.kernel.org/linux-arm-kernel/20240812024141.2867655-1-quic_jiegan@quicinc.com/
> 
> Changes in V3:
> 1. Rename the device to Coresight TMC Control Unit(CTCU).
> 2. Introduce a new way to define the platform related configs. The new
>     structure, qcom_ctcu_config, is used to store configurations specific
>     to a platform. Each platform should have its own qcom_ctcu_config structure.
> 3. In perf mode, the ETM devices allocate their trace IDs using the
>     perf_sink_id_map. In sysfs mode, the ETM devices allocate their trace
>     IDs using the id_map_default.
> 4. Considering the scenario where both ETR devices might be enabled simultaneously
>     with multiple sources, retrieving and using trace IDs instead of id_map is more effective
>     for the CTCU device in sysfs mode. For example, We can configure one ETR as sink for high
>     throughput trace data like ETM and another ETR for low throughput trace data like STM.
>     In this case, STM data won’t be flushed out by ETM data quickly. However, if we use id_map to
>     manage the trace IDs, we need to create a separate id_map for each ETR device. Addtionally, We
>     would need to iterate through the entire id_map for each configuration.
> 5. Add support for apb's clock name "apb". If the function fails to obtain the clock with
>     the name "apb_pclk", it will attempt to acquire the clock with the name "apb".
> Link to V2 - https://lore.kernel.org/linux-arm-msm/20240705090049.1656986-1-quic_jiegan@quicinc.com/T/#t
> 
> Changes in V2:
> 1. Rename the device to Coresight Control Unit.
> 2. Introduce the trace_id function pointer to address the challeng how to
>     properly collect the trace ID of the device.
> 3. Introduce a new way to define the qcom,ccu-atid-offset property in
> device tree.
> 4. Disabling the filter function blocked on acquiring the ATID-offset,
>     which will be addressed in a separate patch once it’s ready.
> Link to V1 - https://lore.kernel.org/lkml/20240618072726.3767974-1-quic_jiegan@quicinc.com/T/#t
> ---
> 
> James Clark (1):
>    Coresight: Use coresight_etm_get_trace_id() in traceid_show()
> 
> Jie Gan (9):
>    Coresight: Add support for new APB clock name
>    Coresight: Add trace_id function to retrieving the trace ID
>    Coresight: Introduce a new struct coresight_path
>    Coresight: Move trace_id to coresight_path and allocate it after
>      building the path
>    Coresight: Change to read the trace ID from coresight_path
>    Coresight: Change functions to accept the coresight_path
>    dt-bindings: arm: Add Coresight TMC Control Unit hardware
>    Coresight: Add Coresight TMC Control Unit driver
>    arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
> 
>   .../bindings/arm/qcom,coresight-ctcu.yaml     |  84 +++++
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi         | 153 ++++++++
>   drivers/hwtracing/coresight/Kconfig           |  12 +
>   drivers/hwtracing/coresight/Makefile          |   2 +
>   drivers/hwtracing/coresight/coresight-core.c  | 122 +++++--
>   .../hwtracing/coresight/coresight-ctcu-core.c | 326 ++++++++++++++++++
>   drivers/hwtracing/coresight/coresight-ctcu.h  |  39 +++
>   drivers/hwtracing/coresight/coresight-dummy.c |  15 +-
>   .../hwtracing/coresight/coresight-etm-perf.c  |  27 +-
>   .../hwtracing/coresight/coresight-etm-perf.h  |   2 +-
>   drivers/hwtracing/coresight/coresight-etm.h   |   1 -
>   .../coresight/coresight-etm3x-core.c          |  55 +--
>   .../coresight/coresight-etm3x-sysfs.c         |   3 +-
>   .../coresight/coresight-etm4x-core.c          |  55 +--
>   .../coresight/coresight-etm4x-sysfs.c         |   4 +-
>   drivers/hwtracing/coresight/coresight-etm4x.h |   1 -
>   drivers/hwtracing/coresight/coresight-priv.h  |  14 +-
>   drivers/hwtracing/coresight/coresight-stm.c   |  13 +-
>   drivers/hwtracing/coresight/coresight-sysfs.c |  17 +-
>   drivers/hwtracing/coresight/coresight-tpda.c  |  11 +
>   drivers/hwtracing/coresight/coresight-tpdm.c  |   2 +-
>   include/linux/coresight.h                     |  27 +-
>   22 files changed, 824 insertions(+), 161 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>   create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-core.c
>   create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
> 

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