linux-kernel - [tip: irq/drivers] irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL

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Message-ID: <174056783756.10177.5053244649280730644.tip-bot2@tip-bot2>
Date: Wed, 26 Feb 2025 11:03:57 -0000
From: "tip-bot2 for Biju Das" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Biju Das <biju.das.jz@...renesas.com>,
 Thomas Gleixner <tglx@...utronix.de>,
 Geert Uytterhoeven <geert+renesas@...der.be>, x86@...nel.org,
 linux-kernel@...r.kernel.org
Subject: [tip: irq/drivers] irqchip/renesas-rzv2h: Update macros
 ICU_TSSR_TSSEL_{MASK,PREP}

The following commit has been merged into the irq/drivers branch of tip:

Commit-ID:     e3a16c33db69ffd1369ebfdf93f93a93a785896a
Gitweb:        https://git.kernel.org/tip/e3a16c33db69ffd1369ebfdf93f93a93a785896a
Author:        Biju Das <biju.das.jz@...renesas.com>
AuthorDate:    Mon, 24 Feb 2025 13:11:27 
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Wed, 26 Feb 2025 11:59:50 +01:00

irqchip/renesas-rzv2h: Update macros ICU_TSSR_TSSEL_{MASK,PREP}

On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H.
Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved
bits is ignored.

Use bitmask GENMASK(field_width - 2, 0) on both SoCs for extracting TSSEL
and then update the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK for
supporting both SoCs.

Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Link: https://lore.kernel.org/all/20250224131253.134199-12-biju.das.jz@bp.renesas.com

---
 drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 8d0bd4d..7bc4397 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,13 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
-#define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
+#define ICU_TSSR_TSSEL_PREP(tssel, n, field_width)	((tssel) << ((n) * (field_width)))
+#define ICU_TSSR_TSSEL_MASK(n, field_width)	\
+({\
+		typeof(field_width) (_field_width) = (field_width); \
+		ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
+})
+
 #define ICU_TSSR_TIEN(n, field_width)	\
 ({\
 		typeof(field_width) (_field_width) = (field_width); \
@@ -326,8 +331,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	guard(raw_spinlock)(&priv->lock);
 
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
-	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
-	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
+	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien);
+	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width);
 
 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));