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Message-ID: <20250227154012.259566-11-c.parant@phytec.fr>
Date: Thu, 27 Feb 2025 16:40:11 +0100
From: Christophe Parant <c.parant@...tec.fr>
To: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Maxime Coquelin
<mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>,
<upstream@...ts.phytec.de>
Subject: [PATCH 10/11] ARM: dts: stm32: phyboard-sargas and phycore: Fix coding style issues
- Remove "stm32-pinfunc.h" include as it is already include in
"stm32mp15-pinctrl.dtsi" file.
- reserved-memory: reorder the memory sections (lower to higher
addresses).
- Move vendor properties (go last).
- Remove useless compatible values:
- QSPI flash: remove the winbond compatible. jedec is enought as the
NOR flahses are detectable.
- EEPROM: "atmel,24c32" is enought.
- Use uppercase for regulator-name properties.
- In pmic node: use the names from the PHYTEC SoM schematics.
- stmpe811 touch: fix dts schema to comply with st,stmpe.yaml.
- Fix one "multiple blank lines" detected by checkpatch.
Signed-off-by: Christophe Parant <c.parant@...tec.fr>
---
.../st/stm32mp157c-phyboard-sargas-rdk.dts | 1 -
.../dts/st/stm32mp15xx-phyboard-sargas.dtsi | 13 ++--
.../boot/dts/st/stm32mp15xx-phycore-som.dtsi | 64 +++++++++----------
3 files changed, 36 insertions(+), 42 deletions(-)
diff --git a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts
index c9870f94ac1f..9a6270e68c6c 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-phycore-som.dtsi"
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi
index 3d62f9e4d0cd..729a97f82538 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi
@@ -5,7 +5,6 @@
* Author: Dom VOVARD <dom.vovard@...rt.com>.
*/
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
@@ -101,13 +100,13 @@ touch@44 {
interrupt-parent = <&gpioi>;
vio-supply = <&v3v3>;
vcc-supply = <&v3v3>;
+ st,sample-time = <4>;
+ st,mod-12b = <1>;
+ st,ref-sel = <0>;
+ st,adc-freq = <1>;
touchscreen {
compatible = "st,stmpe-ts";
- st,sample-time = <4>;
- st,mod-12b = <1>;
- st,ref-sel = <0>;
- st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;
@@ -159,10 +158,10 @@ &sai2 {
&sai2a {
dma-names = "rx";
- st,sync = <&sai2b 2>;
clocks = <&rcc SAI2_K>, <&sai2b>;
clock-names = "sai_ck", "MCLK";
#clock-cells = <0>;
+ st,sync = <&sai2b 2>;
sai2a_port: port {
sai2a_endpoint: endpoint {
@@ -195,9 +194,9 @@ &sdmmc1 {
pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>;
cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
disable-wp;
- st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
+ st,neg-edge;
status = "okay";
};
diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi
index 3f60f184978c..0689967b8c56 100644
--- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi
@@ -36,18 +36,6 @@ reserved-memory {
#size-cells = <1>;
ranges;
- retram: retram@...00000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
-
- mcuram: mcuram@...00000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
mcuram2: mcuram2@...00000 {
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
@@ -71,11 +59,22 @@ vdev0buffer: vdev0buffer@...42000 {
reg = <0x10042000 0x4000>;
no-map;
};
+ mcuram: mcuram@...00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@...00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
};
regulator_vin: regulator {
compatible = "regulator-fixed";
- regulator-name = "vin";
+ regulator-name = "VIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
@@ -102,11 +101,11 @@ phy0: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpiog>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
- enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
@@ -144,7 +143,7 @@ regulators {
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
- regulator-name = "vddcore";
+ regulator-name = "VDD_CORE";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
@@ -152,7 +151,7 @@ vddcore: buck1 {
};
vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
+ regulator-name = "VDD_DDR";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
@@ -160,7 +159,7 @@ vdd_ddr: buck2 {
};
vdd: buck3 {
- regulator-name = "vdd";
+ regulator-name = "VDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
@@ -169,7 +168,7 @@ vdd: buck3 {
};
v3v3: buck4 {
- regulator-name = "v3v3";
+ regulator-name = "VDD_BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
@@ -177,7 +176,7 @@ v3v3: buck4 {
};
v1v8_audio: ldo1 {
- regulator-name = "v1v8_audio";
+ regulator-name = "VDD_LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -186,7 +185,7 @@ v1v8_audio: ldo1 {
};
vdd_eth_2v5: ldo2 {
- regulator-name = "dd_eth_2v5";
+ regulator-name = "VDD_ETH_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
@@ -195,7 +194,7 @@ vdd_eth_2v5: ldo2 {
};
vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
+ regulator-name = "VTT_DDR";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
@@ -203,12 +202,12 @@ vtt_ddr: ldo3 {
};
vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
+ regulator-name = "VDD_USB";
interrupts = <IT_CURLIM_LDO4 0>;
};
vdda: ldo5 {
- regulator-name = "vdda";
+ regulator-name = "VDDA";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
@@ -216,7 +215,7 @@ vdda: ldo5 {
};
vdd_eth_1v0: ldo6 {
- regulator-name = "vdd_eth_1v0";
+ regulator-name = "VDD_ETH_1V0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -225,23 +224,23 @@ vdd_eth_1v0: ldo6 {
};
vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
+ regulator-name = "VDD_REFDDR";
regulator-always-on;
};
bst_out: boost {
- regulator-name = "bst_out";
+ regulator-name = "BST_OUT";
interrupts = <IT_OCP_BOOST 0>;
};
vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
+ regulator-name = "VBUS_OTG";
interrupts = <IT_OCP_OTG 0>;
regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
+ regulator-name = "VBUS_SW";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
@@ -262,8 +261,7 @@ watchdog {
};
i2c4_eeprom: eeprom@50 {
- compatible = "microchip,24c32",
- "atmel,24c32";
+ compatible = "atmel,24c32";
reg = <0x50>;
status = "disabled";
};
@@ -312,13 +310,11 @@ &qspi_bk1_sleep_pins_a
status = "disabled";
flash0: flash@0 {
- compatible = "winbond,w25q128", "jedec,spi-nor";
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
m25p,fast-read;
- #address-cells = <1>;
- #size-cells = <1>;
};
};
@@ -342,10 +338,10 @@ &sdmmc2 {
non-removable;
no-sd;
no-sdio;
- st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
mmc-ddr-3_3v;
+ st,neg-edge;
status = "disabled";
};
--
2.34.1
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