linux-kernel - Re: [PATCH v2 2/8] drm/msm/dpu: program master INTF value

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Message-ID: <CAACA6C8-441A-4B6E-AC07-A46094A02126@somainline.org>
Date: Fri, 28 Feb 2025 10:23:54 +0100
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
 Rob Clark <robdclark@...il.com>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
 Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
 Simona Vetter <simona@...ll.ch>
CC: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/8] drm/msm/dpu: program master INTF value

On 28 February 2025 05:14:06 CET, Dmitry Baryshkov <dmitry.baryshkov@...aro.org> wrote:
>If several interfaces are being handled through a single CTL, a main
>('master') INTF needs to be programmed into a separate register. Write
>corresponding value into that register.
>
>Co-developed-by: Marijn Suijten <marijn.suijten@...ainline.org>
>Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
>Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 12 ++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  2 ++
> 2 files changed, 14 insertions(+)
>
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>index 32ab33b314fc44e12ccb935c1695d2eea5c7d9b2..ffff60c4206c6f2833293fdcc56b653f7d3124a5 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>@@ -583,6 +583,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> 	DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
> 	DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
> 
>+	if (cfg->intf_master)
>+		DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0));
>+
> 	if (cfg->cdm)
> 		DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);
> }
>@@ -625,6 +628,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> {
> 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> 	u32 intf_active = 0;
>+	u32 intf_master = 0;
> 	u32 wb_active = 0;
> 	u32 merge3d_active = 0;
> 	u32 dsc_active;
>@@ -651,6 +655,14 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> 		intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
> 		intf_active &= ~BIT(cfg->intf - INTF_0);
> 		DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
>+
>+		intf_master = DPU_REG_READ(c, CTL_INTF_MASTER);
>+
>+		/* Unset this intf as master, if it is the current master */
>+		if (intf_master == BIT(cfg->intf - INTF_0)) {
>+			DPU_DEBUG_DRIVER("Unsetting INTF_%d master\n", cfg->intf - INTF_0);

Don't think you want to include my testing ramblings here: we didn't print a message either when the master was _set_, and don't print messages for other register writes either.

After that:

Reviewed-by: Marijn Suijten <marijn.suijten@...ainline.org>

>+			DPU_REG_WRITE(c, CTL_INTF_MASTER, 0);
>+		}
> 	}
> 
> 	if (cfg->wb) {
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
>index 85c6c835cc8780e6cb66f3a262d9897c91962935..e95989a2fdda6344d0cb9d3036e6ed22a0458675 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
>@@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg {
> /**
>  * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
>  * @intf :                 Interface id
>+ * @intf_master:           Master interface id in the dual pipe topology

Not sure if you've seen my comment in v1 about the dual word; maybe the quadpipe series can update it since they might need a master (or two?) as well?

- Marijn

>  * @mode_3d:               3d mux configuration
>  * @merge_3d:              3d merge block used
>  * @intf_mode_sel:         Interface mode, cmd / vid
>@@ -45,6 +46,7 @@ struct dpu_hw_stage_cfg {
>  */
> struct dpu_hw_intf_cfg {
> 	enum dpu_intf intf;
>+	enum dpu_intf intf_master;
> 	enum dpu_wb wb;
> 	enum dpu_3d_blend_mode mode_3d;
> 	enum dpu_merge_3d merge_3d;
>