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Message-ID: <20250304172743.0000211e@huawei.com>
Date: Tue, 4 Mar 2025 17:27:43 +0800
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Yicong Yang <yangyicong@...wei.com>
CC: <will@...nel.org>, <mark.rutland@....com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<prime.zeng@...ilicon.com>, <linuxarm@...wei.com>,
<yangyicong@...ilicon.com>, <wangyushan12@...wei.com>
Subject: Re: [PATCH 3/9] drivers/perf: hisi: Add support for HiSilicon DDRC
v3 PMU driver
On Tue, 18 Feb 2025 17:19:54 +0800
Yicong Yang <yangyicong@...wei.com> wrote:
> From: Junhao He <hejunhao3@...wei.com>
>
> HiSilicon DDRC v3 PMU has the different interrupt register offset
> compared to the v2. Add device information of v3 PMU with ACPI
> HID HISI0235.
>
> Signed-off-by: Junhao He <hejunhao3@...wei.com>
> Signed-off-by: Yicong Yang <yangyicong@...ilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
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