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Message-ID: <20250306152451.2356762-3-thierry.bultel.yh@bp.renesas.com>
Date: Thu, 6 Mar 2025 16:24:36 +0100
From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
To: thierry.bultel@...atsea.fr
Cc: linux-renesas-soc@...r.kernel.org,
geert@...ux-m68k.org,
paul.barker.ct@...renesas.com,
Thierry Bultel <thierry.bultel.yh@...renesas.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v4 02/13] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC
Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
---
Changes v3->v4:
- Handle maxItems and clocks names properly in schema.
---
.../bindings/clock/renesas,cpg-mssr.yaml | 56 +++++++++++++------
.../clock/renesas,r9a09g077-cpg-mssr.h | 49 ++++++++++++++++
2 files changed, 89 insertions(+), 16 deletions(-)
create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 77ce3615c65a..acbb555a064e 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -52,9 +52,10 @@ properties:
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
+ - renesas,r9a09g077-cpg-mssr # RZ/T2H
reg:
- maxItems: 1
+ description: Registers base address
clocks:
minItems: 1
@@ -63,11 +64,6 @@ properties:
clock-names:
minItems: 1
maxItems: 2
- items:
- enum:
- - extal # All
- - extalr # Most R-Car Gen3 and RZ/G2
- - usb_extal # Most R-Car Gen2 and RZ/G1
'#clock-cells':
description: |
@@ -92,16 +88,6 @@ properties:
the datasheet.
const: 1
-if:
- not:
- properties:
- compatible:
- items:
- enum:
- - renesas,r7s9210-cpg-mssr
-then:
- required:
- - '#reset-cells'
required:
- compatible
@@ -113,6 +99,44 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-cpg-mssr
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: extal
+ - const: loco
+ else:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ enum:
+ - extal # All
+ - extalr # Most R-Car Gen3 and RZ/G2
+ - usb_extal # Most R-Car Gen2 and RZ/G1
+
+ - if:
+ not:
+ properties:
+ compatible:
+ items:
+ enum:
+ - renesas,r7s9210-cpg-mssr
+ then:
+ required:
+ - '#reset-cells'
+
examples:
- |
cpg: clock-controller@...50000 {
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
new file mode 100644
index 000000000000..27c9cdcdf7c8
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G077 CPG Core Clocks */
+#define R9A09G077_CA55C0 0
+#define R9A09G077_CA55C1 1
+#define R9A09G077_CA55C2 2
+#define R9A09G077_CA55C3 3
+#define R9A09G077_SDHIHS 4
+#define R9A09G077_CLK_PLL1_ETH_PHY 5
+#define R9A09G077_CLK_OSC_ETH_PHY 6
+#define R9A09G077_CLK_ETHPHY 7
+#define R9A09G077_PCLKAH 8
+#define R9A09G077_PCLKAM 9
+#define R9A09G077_PCLKAL 10
+#define R9A09G077_CLK_SEL_ETH_PHY 11
+#define R9A09G077_DFI 12
+#define R9A09G077_PCLKH 13
+#define R9A09G077_PCLKM 14
+#define R9A09G077_PCLKL 15
+#define R9A09G077_PCLKGPTL 16
+#define R9A09G077_PCLKSHOST 17
+#define R9A09G077_PCLKRTC 18
+#define R9A09G077_USB 19
+#define R9A09G077_SPI0 20
+#define R9A09G077_SPI1 21
+#define R9A09G077_SPI2 22
+#define R9A09G077_SPI3 23
+#define R9A09G077_ETCLKA 24
+#define R9A09G077_ETCLKB 25
+#define R9A09G077_ETCLKC 26
+#define R9A09G077_ETCLKD 27
+#define R9A09G077_ETCLKE 28
+#define R9A09G077_ETHCLKE 29
+#define R9A09G077_ETHCLK_EXTAL 30
+#define R9A09G077_ETH_REFCLK 31
+#define R9A09G077_LCDC_CLKA 32
+#define R9A09G077_LCDC_CLKP 33
+#define R9A09G077_CA55 34
+#define R9A09G077_LCDC_CLKD 35
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
--
2.43.0
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