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Message-ID: <Z8meY7NS65_d14og@smile.fi.intel.com>
Date: Thu, 6 Mar 2025 15:08:51 +0200
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: mailhol.vincent@...adoo.fr
Cc: Yury Norov <yury.norov@...il.com>,
Lucas De Marchi <lucas.demarchi@...el.com>,
Rasmus Villemoes <linux@...musvillemoes.dk>,
Jani Nikula <jani.nikula@...ux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@...el.com>,
Tvrtko Ursulin <tursulin@...ulin.net>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Andrew Morton <akpm@...ux-foundation.org>,
linux-kernel@...r.kernel.org, intel-gfx@...ts.freedesktop.org,
dri-devel@...ts.freedesktop.org,
Andi Shyti <andi.shyti@...ux.intel.com>,
David Laight <David.Laight@...lab.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Jani Nikula <jani.nikula@...el.com>
Subject: Re: [PATCH v5 2/7] bits: introduce fixed-type genmasks
On Thu, Mar 06, 2025 at 08:29:53PM +0900, Vincent Mailhol via B4 Relay wrote:
> From: Yury Norov <yury.norov@...il.com>
>
> Add GENMASK_TYPE() which generalizes __GENMASK() to support different
> types, and implement fixed-types versions of GENMASK() based on it.
> The fixed-type version allows more strict checks to the min/max values
> accepted, which is useful for defining registers like implemented by
> i915 and xe drivers with their REG_GENMASK*() macros.
>
> The strict checks rely on shift-count-overflow compiler check to fail
> the build if a number outside of the range allowed is passed.
> Example:
>
> #define FOO_MASK GENMASK_U32(33, 4)
>
> will generate a warning like:
>
> include/linux/bits.h:51:27: error: right shift count >= width of type [-Werror=shift-count-overflow]
> 51 | type_max(t) >> (BITS_PER_TYPE(t) - 1 - (h)))))
> | ^~
Code LGTM, but just to be sure: you prepared your series using histogram
diff algo, right?
--
With Best Regards,
Andy Shevchenko
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