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Message-ID: <1994155.PYKUYFuaPT@jernej-laptop>
Date: Sun, 09 Mar 2025 08:00:20 +0100
From: Jernej Škrabec <jernej.skrabec@...il.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...e.org>, Samuel Holland <samuel@...lland.org>,
Andre Przywara <andre.przywara@....com>
Cc: Philipp Zabel <p.zabel@...gutronix.de>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 13/14] clk: sunxi-ng: a523: add reset lines
Dne petek, 7. marec 2025 ob 01:26:27 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> Allwinner SoCs do not contain a separate reset controller, instead the
> reset lines for the various devices are integrated into the "BGR" (Bus
> Gate / Reset) registers, for each device group: one for all UARTs, one
> for all SPI interfaces, and so on.
> The Allwinner CCU driver also doubles as a reset provider, and since the
> reset lines are indeed just single bits in those BGR register, we can
> represent them easily in an array of structs, just containing the
> register offset and the bit number.
>
> Add the location of the reset bits for all devices in the A523/T527
> SoCs, using the existing sunxi CCU infrastructure.
>
> Signed-off-by: Andre Przywara <andre.przywara@....com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@...il.com>
Best regards,
Jernej
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