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Date: Wed, 12 Mar 2025 13:51:15 +0000
From: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
To: Conor Dooley <conor@...nel.org>
CC: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>, Paul Walmsley
<paul.walmsley@...ive.com>, Samuel Holland <samuel.holland@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>, Min Lin
<linmin@...incomputing.com>, Pritesh Patel <pritesh.patel@...fochips.com>,
Yangyu Chen <cyy@...self.name>, Lad Prabhakar
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Shilledar <kanakshilledar@...il.com>, Darshan Prajapati
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<anup@...infault.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-riscv@...ts.infradead.org"
<linux-riscv@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
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Subject: RE: [External] Re: [PATCH 05/10] dt-bindings: cache: sifive,ccache0:
Add ESWIN EIC7700 SoC compatibility
Hi Conor,
On Tue, Mar 11, 2025 at 06:11:43PM +0530, Conor Dooley wrote:
> On Tue, Mar 11, 2025 at 01:04:27PM +0530, Pinkesh Vaghela wrote:
> > From: Pritesh Patel <pritesh.patel@...fochips.com>
> >
> > This cache controller is also used on the ESWIN EIC7700 SoC.
> > However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
> > So add dedicated compatible string for it.
> >
> > Signed-off-by: Pritesh Patel <pritesh.patel@...fochips.com>
> > Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
> > ---
> > .../bindings/cache/sifive,ccache0.yaml | 28 +++++++++++++++++--
> > 1 file changed, 25 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> > b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> > index 7e8cebe21584..11e9df2cd153 100644
> > --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> > +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> > @@ -39,6 +39,7 @@ properties:
> > - const: cache
> > - items:
> > - enum:
> > + - eswin,eic7700-l3-cache
> > - starfive,jh7100-ccache
> > - starfive,jh7110-ccache
> > - const: sifive,ccache0
> > @@ -55,10 +56,10 @@ properties:
> > enum: [2, 3]
> >
> > cache-sets:
> > - enum: [1024, 2048]
> > + enum: [1024, 2048, 4096]
> >
> > cache-size:
> > - const: 2097152
> > + enum: [2097152, 4194304]
>
> Making this an enum makes either value permitted on each SoC. Can you add
> cache-size restrictions to the if statements below to keep it restricted to the
> correct value please?
>
> Cheers,
> Conor.
Thanks for the feedback. I will address this in v2.
Regards,
Pinkesh
>
> >
> > cache-unified: true
> >
> > @@ -89,6 +90,7 @@ allOf:
> > compatible:
> > contains:
> > enum:
> > + - eswin,eic7700-l3-cache
> > - sifive,fu740-c000-ccache
> > - starfive,jh7100-ccache
> > - starfive,jh7110-ccache @@ -122,11 +124,31 @@ allOf:
> > cache-sets:
> > const: 2048
> >
> > - else:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - microchip,mpfs-ccache
> > + - sifive,fu540-c000-ccache
> > +
> > + then:
> > properties:
> > cache-sets:
> > const: 1024
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - eswin,eic7700-l3-cache
> > +
> > + then:
> > + properties:
> > + cache-sets:
> > + const: 4096
> > +
> > - if:
> > properties:
> > compatible:
> > --
> > 2.25.1
> >
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