linux-kernel - RE: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X only configuration.

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Message-ID:
 <BL3PR12MB6571795DA783FD05189AD74BC9D02@BL3PR12MB6571.namprd12.prod.outlook.com>
Date: Wed, 12 Mar 2025 14:49:05 +0000
From: "Gupta, Suraj" <Suraj.Gupta2@....com>
To: Russell King <linux@...linux.org.uk>, Andrew Lunn <andrew@...n.ch>
CC: "Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>,
	"andrew+netdev@...n.ch" <andrew+netdev@...n.ch>, "davem@...emloft.net"
	<davem@...emloft.net>, "edumazet@...gle.com" <edumazet@...gle.com>,
	"kuba@...nel.org" <kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>, "Simek,
 Michal" <michal.simek@....com>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "git (AMD-Xilinx)" <git@....com>,
	"Katakam, Harini" <harini.katakam@....com>
Subject: RE: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X
 only configuration.

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Russell King <linux@...linux.org.uk>
> Sent: Wednesday, March 12, 2025 7:44 PM
> To: Andrew Lunn <andrew@...n.ch>
> Cc: Gupta, Suraj <Suraj.Gupta2@....com>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@....com>; andrew+netdev@...n.ch;
> davem@...emloft.net; edumazet@...gle.com; kuba@...nel.org;
> pabeni@...hat.com; robh@...nel.org; krzk+dt@...nel.org; conor+dt@...nel.org;
> Simek, Michal <michal.simek@....com>; netdev@...r.kernel.org;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; git (AMD-Xilinx) <git@....com>; Katakam, Harini
> <harini.katakam@....com>
> Subject: Re: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X only
> configuration.
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On Wed, Mar 12, 2025 at 02:25:27PM +0100, Andrew Lunn wrote:
> > > +   /* AXI 1G/2.5G ethernet IP has following synthesis options:
> > > +    * 1) SGMII/1000base-X only.
> > > +    * 2) 2500base-X only.
> > > +    * 3) Dynamically switching between (1) and (2), and is not
> > > +    * implemented in driver.
> > > +    */
> > > +
> > > +   if (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_2_5G)
> >
> > How can we tell if the synthesis allows 3)?
> >
> > Don't we have a backwards compatibility issue here? Maybe there are
> > systems which have been synthesised with 3), but are currently limited
> > to 1) due to the driver. If you don't differentiate between 2 and 3,
> > such systems are going to swap to 2) and regress.
>
> We've discussed this before... but because the author doesn't post regularly enough,
> it's not suprising that context keeps getting lost.
>
> Here's the discussion from 20th February 2025 on a patch series that I commented
> on on 19th November 2024.
>
> https://lore.kernel.org/r/BL3PR12MB6571FE73FA8D5AAB9FB4BB3CC9C42@BL3
> PR12MB6571.namprd12.prod.outlook.com
>
> Suraj Gupta - you _must_ be more responsive so that reviewers can keep the
> context of previous discussions in their heads to avoid going over the same points
> time and time again. If you can't do that (and it's a good idea anyway) then you need
> to supplement the commit descriptions with the salient points from the previous
> patch series discussion to remind reviewers of the appropriate context.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Thanks Russell, sure I'll add salient points from previous discussions if it becomes old (won't try to delay at first).
Andrew - Keeping previous discussion short, identification of (3) depends on how user implements switching logic in FPGA (external GT or RTL logic). AXI 1G/2.5G IP provides only static speed selections and there is no standard register to communicate that to software.