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Message-ID: <ujqeq5do2xqf5jvepxaynaxridccalbjows7gid4ehyj7jduyk@2axt2thtet6z>
Date: Thu, 13 Mar 2025 22:34:25 +0800
From: Zixian Zeng <sycamoremoon376@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Chen Wang <unicorn_wang@...look.com>,
Inochi Amaoto <inochiama@...look.com>, Alexandre Ghiti <alex@...ti.fr>, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, sophgo@...ts.linux.dev,
chao.wei@...hgo.com, xiaoguang.xing@...hgo.com, dlan@...too.org
Subject: Re: [PATCH v3 2/2] riscv: sophgo: dts: Add spi controller for SG2042
On 25/03/13 02:43PM, Krzysztof Kozlowski wrote:
> On 13/03/2025 14:11, Zixian Zeng wrote:
> > Add spi controllers for SG2042.
> >
> > SG2042 uses the upstreamed Synopsys DW SPI IP.
> >
> > Signed-off-by: Zixian Zeng <sycamoremoon376@...il.com>
> > ---
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > index e62ac51ac55abd922b5ef796ba8c2196383850c4..9e0ec64e91a2330698aea202c8f0a2ca1f7e0919 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -545,5 +545,31 @@ sd: mmc@...002b000 {
> > "timer";
> > status = "disabled";
> > };
> > +
> > + spi0: spi@...0004000 {
>
> Does not look like you keep order by unit address (see DTS coding style).
>
Thanks for reminding, I will read it more carefully.
>
> Best regards,
> Krzysztof
Best regards,
Zixian Zeng
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