linux-kernel - Re: [PATCH v10] net: mdio: Add RTL9300 MDIO driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6ae8b7c6-8e75-4bfc-9ea3-302269a26951@alliedtelesis.co.nz>
Date: Thu, 13 Mar 2025 20:44:10 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Andrew Lunn <andrew@...n.ch>
CC: "hkallweit1@...il.com" <hkallweit1@...il.com>, "linux@...linux.org.uk"
	<linux@...linux.org.uk>, "davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>, "kuba@...nel.org"
	<kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"daniel@...rotopia.org" <daniel@...rotopia.org>, "markus.stockhausen@....de"
	<markus.stockhausen@....de>, "sander@...nheule.net" <sander@...nheule.net>,
	netdev <netdev@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v10] net: mdio: Add RTL9300 MDIO driver


On 14/03/2025 09:40, Andrew Lunn wrote:
> On Thu, Mar 13, 2025 at 08:37:18PM +0000, Chris Packham wrote:
>> On 14/03/2025 09:35, Andrew Lunn wrote:
>>> On Thu, Mar 13, 2025 at 07:54:39PM +0000, Chris Packham wrote:
>>>> +cc netdev, lkml
>>>>
>>>> On 14/03/2025 01:34, Andrew Lunn wrote:
>>>>>> +	/* Put the interfaces into C45 mode if required */
>>>>>> +	glb_ctrl_mask = GENMASK(19, 16);
>>>>>> +	for (i = 0; i < MAX_SMI_BUSSES; i++)
>>>>>> +		if (priv->smi_bus_is_c45[i])
>>>>>> +			glb_ctrl_val |= GLB_CTRL_INTF_SEL(i);
>>>>>> +
>>>>>> +	fwnode_for_each_child_node(node, child)
>>>>>> +		if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45"))
>>>>>> +			priv->smi_bus_is_c45[mdio_bus] = true;
>>>>>> +
>>>>> This needs more explanation. Some PHYs mix C22 and C45, e.g. the > 1G
>>>>> speed support registers are in the C45 address space, but <= 1G is in
>>>>> the C22 space. And 1G PHYs which support EEE need access to C45 space
>>>>> for the EEE registers.
>>>> Ah good point. The MDIO interfaces are either in GPHY (i.e. clause 22)
>>>> or 10GPHY mode (i.e. clause 45). This does mean we can't support support
>>>> both c45 and c22 on the same MDIO bus (whether that's one PHY that
>>>> supports both or two different PHYs). I'll add a comment to that effect
>>>> and I should probably only provide bus->read/write or
>>>> bus->read_c45/write_c45 depending on the mode.
>>> Is there more to it than this? Because why not just set the mode per
>>> bus transaction?
>> It's a bus level setting at init time. You can't dynamically switch modes.
> Why not? The bus is only every doing one transaction at a time, so why
> not switch it per transaction?

I'm pretty sure it would upset the hardware polling mechanism which 
unfortunately we can't disable (earlier I thought we could but there are 
various switch features that rely on it).