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Message-ID: <363bdb81-d26e-4f1a-969e-c5ee682cf044@alliedtelesis.co.nz>
Date: Thu, 13 Mar 2025 22:53:20 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Andrew Lunn <andrew@...n.ch>
CC: "hkallweit1@...il.com" <hkallweit1@...il.com>, "linux@...linux.org.uk"
	<linux@...linux.org.uk>, "davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>, "kuba@...nel.org"
	<kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"daniel@...rotopia.org" <daniel@...rotopia.org>, "markus.stockhausen@....de"
	<markus.stockhausen@....de>, "sander@...nheule.net" <sander@...nheule.net>,
	netdev <netdev@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v10] net: mdio: Add RTL9300 MDIO driver


On 14/03/2025 11:07, Andrew Lunn wrote:
>> I'm pretty sure it would upset the hardware polling mechanism which
>> unfortunately we can't disable (earlier I thought we could but there are
>> various switch features that rely on it).
> So we need to get a better understanding of that polling. How are you
> telling it about the aquantia PHY features? How does it know it needs
> to get the current link rate from MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1
> which is a vendor register, not a standard C45 register? How do you
> teach it to decode bits in that register?

The hardware polling for C45 PHYs is reasonably configurable so I think 
you can define which MMD device/register to look at and what bit masks 
to apply to determine the link status. I think when we get to a complete 
switch driver (hoping for switchdev but could be dsa) it may need to 
know some details about the specific PHY that is attached and have some 
way of telling the mdio controller about this.

Right now I'm focusing on a platform that is RTL9300 + RTL8224 (clause 
45) so the defaults mostly just work. I do have one of the Zyxel boards 
with an AQR PHY but haven't been able to root it yet (Markus gave me 
some tips for that just haven't tried them yet).

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