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Message-ID: <88b3ecbe-32b6-4310-afb9-da19a2d0506a@bootlin.com>
Date: Fri, 14 Mar 2025 10:03:01 +0100
From: Thomas Richard <thomas.richard@...tlin.com>
To: Siddharth Vadapalli <s-vadapalli@...com>, lpieralisi@...nel.org,
kw@...ux.com, manivannan.sadhasivam@...aro.org, robh@...nel.org,
bhelgaas@...gle.com, vigneshr@...com, kishon@...nel.org, cassel@...nel.org,
wojciech.jasko-EXT@...tinental-corporation.com, bwawrzyn@...co.com
Cc: linux-pci@...r.kernel.org, linux-omap@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
srk@...com
Subject: Re: [PATCH 4/4] PCI: j721e: Add support to build as a loadable module
> +
> + if (pcie->reset_gpio) {
> + msleep(PCIE_T_PVPERL_MS);
> + gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> + }
> +
> + if (pcie->refclk)
> + clk_disable_unprepare(pcie->refclk);
>
Hello Siddharth,
I think clk_disable_unprepare() is a no-op if the clock is NULL, so the
if statement is useless.
https://elixir.bootlin.com/linux/v6.14-rc6/source/include/linux/clk.h#L1157
https://elixir.bootlin.com/linux/v6.14-rc6/source/drivers/clk/clk.c#L1237
https://elixir.bootlin.com/linux/v6.14-rc6/source/drivers/clk/clk.c#L1099
Regards,
Thomas
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