linux-kernel - Re: [PATCH v2 3/5] clk: renesas: rzv2h-cpg: Add support for enabling PLLs

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Message-ID: <CA+V-a8vM+jcs3j6MYfM1tUK7USvSrCBYqh+hRFnaPq9d_jRdwQ@mail.gmail.com>
Date: Fri, 14 Mar 2025 13:47:59 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>, Michael Turquette <mturquette@...libre.com>, 
	Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-renesas-soc@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 3/5] clk: renesas: rzv2h-cpg: Add support for enabling PLLs

Hi Geert,

Thank you for the review.

On Fri, Mar 14, 2025 at 1:04 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 10 Mar 2025 at 19:22, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > On Sun, Mar 9, 2025 at 9:14 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Some RZ/V2H(P) SoC variants do not have a GPU, resulting in PLLGPU being
> > > disabled by default in TF-A. Add support for enabling PLL clocks in the
> > > RZ/V2H(P) CPG driver to manage this.
> > >
> > > Introduce `is_enabled` and `enable` callbacks to handle PLL state
> > > transitions. With the `enable` callback, PLLGPU will be turned ON only
> > > when the GPU node is enabled; otherwise, it will remain off. Define new
> > > macros for PLL standby and monitor registers to facilitate this process.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > ---
> > > v1->v2
> > > - Updated macros to get PLL offsets
> > > - Switched to readl_poll_timeout_atomic() and updated the timeout
>
> Thanks for the update!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> > > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > > +++ b/drivers/clk/renesas/rzv2h-cpg.c
>
> > > +static int rzv2h_cpg_pll_clk_enable(struct clk_hw *hw)
> > > +{
> > > +       struct pll_clk *pll_clk = to_pll(hw);
> > > +       struct rzv2h_cpg_priv *priv = pll_clk->priv;
> > > +       struct pll pll = pll_clk->pll;
> > > +       u32 stby_offset;
> > > +       u32 mon_offset;
> > > +       u32 val;
> > > +       int ret;
> > > +
> > > +       if (rzv2h_cpg_pll_clk_is_enabled(hw))
> > > +               return 0;
> > > +
> > > +       stby_offset = CPG_PLL_STBY(pll.offset);
> > > +       mon_offset = CPG_PLL_MON(pll.offset);
> > > +
> > > +       writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB,
> > > +              priv->base + stby_offset);
> > > +
> > > +       /* ensure PLL is in normal mode */
> > > +       ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
> > > +                                       (val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) ==
> > > +                                       (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK), 10, 100);
> > This timeout didnt work when I power cycled after a complete shutdown overnight.
> >
> > I will update the timeout as below, this Ive made sure the below delay
> > works OK after complete shutdown.
> >
> > /*
> > * Ensure PLL enters into normal mode
> > *
> > * Note: There is no HW information about the worst case latency.
> > *
> > * Since this value might be dependent on external xtal rate, pll
> > * rate or even the other emulation clocks rate, use 2000 as a
> > * "super" safe value.
> > */
> > ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
> >                                                     (val &
> > (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) ==
> >
> > (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK), 200, 2000);
> >
> > Please let me know shall I send v3 with this change or wait for your review.
>
> I can incorporate this fix while queuing in renesas-clk for v6.16.
> But, please explain what is "the other emulation clocks rate"?
>
I got carried away referring to R-Car code, let's drop the `or even
the other emulation clocks rate`. Thank you for taking care of it.

Cheers,
Prabhakar