linux-kernel - Re: [PATCH v2 1/5] clk: renesas: rzv2h: Refactor PLL configuration handling

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Message-ID: <CA+V-a8uhJPssjTsKPwfh7G7P26uuRj+xy_uZF6SQPPQOTx33-A@mail.gmail.com>
Date: Fri, 14 Mar 2025 13:26:03 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 1/5] clk: renesas: rzv2h: Refactor PLL configuration handling

Hi Geert,

Thank you for the review.

On Fri, Mar 14, 2025 at 1:04 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sun, 9 Mar 2025 at 22:14, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Refactor PLL handling by introducing a `struct pll` to encapsulate PLL
> > configuration parameters, ensuring consistency with the existing dynamic
> > divider structure.
> >
> > Introduce the `PLL_PACK()` macro to simplify PLL structure initialization
> > and update the `DEF_PLL()` macro to use the new `pll` structure. Modify
> > relevant clock register functions to utilize the structured PLL data
> > instead of raw configuration values.
> >
> > This refactoring improves code readability, maintainability, and
> > alignment with the existing clock configuration approach.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> i.e. will queue in renesas-clk for v6.16.
>
> > --- a/drivers/clk/renesas/rzv2h-cpg.h
> > +++ b/drivers/clk/renesas/rzv2h-cpg.h
> > @@ -10,6 +10,25 @@
> >
> >  #include <linux/bitfield.h>
> >
> > +/**
> > + * struct pll - Structure for PLL configuration
> > + *
> > + * @offset: STBY register offset
> > + * @clk: Flag to indicate if CLK1/2 are accessible or not
>
> If you don't mind, I'll rename this to "has_clkn" while applying.
>
sounds good to me, thank you for taking care of it.

Cheers,
Prabhakar