linux-kernel - Re: [PATCH v2] openrisc: Add cacheinfo support

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Message-ID: <CAMuHMdWh=oo6JykPGD3DNEL=GcfgyKw2UK7vb8XMbH19GcdrwA@mail.gmail.com>
Date: Mon, 17 Mar 2025 09:25:26 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Stafford Horne <shorne@...il.com>
Cc: Sahil Siddiq <icegambit91@...il.com>, jonas@...thpole.se, 
	stefan.kristiansson@...nalahti.fi, linux-openrisc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Sahil Siddiq <sahilcdq@...ton.me>
Subject: Re: [PATCH v2] openrisc: Add cacheinfo support

Hi Stafford,

On Sun, 16 Mar 2025 at 07:59, Stafford Horne <shorne@...il.com> wrote:
> On Sun, Mar 16, 2025 at 02:09:37AM +0530, Sahil Siddiq wrote:
> > Add cacheinfo support for OpenRISC.
> >
> > Currently, a few CPU cache attributes pertaining to OpenRISC processors
> > are exposed along with other unrelated CPU attributes in the procfs file
> > system (/proc/cpuinfo). However, a few cache attributes remain unexposed.
> > An attempt is also made to pull these CPU cache attributes without
> > detecting if the relevant cache exists.
> >
> > This patch provides a mechanism that the generic cacheinfo infrastructure
> > can employ to expose these attributes via the sysfs file system. These
> > attributes are exposed in /sys/devices/system/cpu/cpuX/cache/indexN.
> > Cache attributes are pulled only when the cache component is detected.
> >
> > The implementation to pull cache attributes from the processor's
> > registers has been moved from arch/openrisc/kernel/setup.c with a few
> > modifications.
> >
> > The patch also moves cache-related fields out of struct cpuinfo_or1k and
> > into its own struct to keep the implementation straightforward. This
> > reduces duplication of cache-related fields while keeping cpuinfo_or1k
> > extensible in case more cache descriptors are added in the future.
> >
> > This implementation is based on similar work done for MIPS and LoongArch.
> >
> > Signed-off-by: Sahil Siddiq <sahilcdq@...ton.me>

> > --- a/arch/openrisc/include/asm/cpuinfo.h
> > +++ b/arch/openrisc/include/asm/cpuinfo.h
> > @@ -15,16 +15,18 @@
> >  #ifndef __ASM_OPENRISC_CPUINFO_H
> >  #define __ASM_OPENRISC_CPUINFO_H
> >
> > +struct cache_desc {
> > +     u32 size;
> > +     u32 sets;
> > +     u32 block_size;
> > +     u32 ways;
>
> Considering the changes below to add cache available checks, maybe we
> want to add a field here, such as `bool present`.  Or a flags field like
> is used in loongarch?

I assume cache_desc.size is zero when the cache is not present?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds