linux-kernel - Re: [PATCH v1] arm64: dts: qcom: ipq5424: fix and relocate uart1 gpio configurations

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <a1cbab24-d931-4946-ba58-4c37f0bb9cc0@quicinc.com>
Date: Mon, 17 Mar 2025 14:52:40 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@....qualcomm.com>,
        <andersson@...nel.org>, <konradybcio@...nel.org>, <robh@...nel.org>,
        <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <quic_srichara@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: <quic_varada@...cinc.com>
Subject: Re: [PATCH v1] arm64: dts: qcom: ipq5424: fix and relocate uart1 gpio
 configurations



On 3/12/2025 10:10 PM, Kathiravan Thirumoorthy wrote:
> On 3/12/2025 2:44 PM, Manikanta Mylavarapu wrote:
>> Update the bias configuration for UART1 TX and RX pins to ensure correct
>> settings for RDP466.
>>
>> Additionally, move the UART1 GPIO configurations from the common .dtsi
>> file to the RDP-specific .dts files to account for differing bias
>> configurations across RDPs of IPQ5424.
>>
>> Fixes: 1a91d2a6021e ("arm64: dts: qcom: add IPQ5424 SoC and rdp466 board support")
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 16 +++++++++++++++-
>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi       |  7 -------
>>   2 files changed, 15 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
>> index b6e4bb3328b3..7b85aaa11ee8 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
>> @@ -147,10 +147,24 @@ data-pins {
>>               bias-pull-up;
>>           };
>>       };
>> +
>> +    uart1_tx_state: uart1-tx-state {
>> +        pins = "gpio44";
>> +        function = "uart1";
>> +        drive-strength = <8>;
>> +        bias-pull-down;
>> +    };
>> +
>> +    uart1_rx_state: uart1-rx-state {
>> +        pins = "gpio43";
>> +        function = "uart1";
>> +        drive-strength = <8>;
>> +        bias-pull-up;
>> +    };
>>   };
>>     &uart1 {
>> -    pinctrl-0 = <&uart1_pins>;
>> +    pinctrl-0 = <&uart1_tx_state>, <&uart1_rx_state>;
> 
> 
> Change LGTM. But can we define both TX and RX pin definition under one node like below, to align with the SPI and SDCC gpio definition layout?
> 
> qup_uart1_default_state: qup-uart1-default-state {
> 
>         uart1_tx_state: uart1-tx-state {
> 
>          ...
> 
>         };
> 
>         uart1_rx_state: uart1-rx-state {
> 
>          ...
> 
>         };
> 
> };
> 
> and refer it like pinctrl-0 = <&qup_uart1_default_state>;
> 
> 

Hi Kathir,

	Thank you for reviewing the patch.
	I will incorporate the suggested change in the next version.

Thanks & Regards,
Manikanta.