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Message-ID: <174218015887.1913428.16257360641397675945.b4-ty@kernel.org>
Date: Sun, 16 Mar 2025 21:55:55 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Jagadeesh Kona <quic_jkona@...cinc.com>
Cc: Ajit Pandey <quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
Taniya Das <quic_tdas@...cinc.com>,
Satya Priya Kakitapalli <quic_skakitap@...cinc.com>,
linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Shivnandan Kumar <quic_kshivnan@...cinc.com>
Subject: Re: [PATCH v2 0/2] Add support to scale DDR and L3 on SA8775P
On Tue, 12 Nov 2024 18:14:10 +0530, Jagadeesh Kona wrote:
> Add support to scale DDR and L3 frequencies
> based on CPU frequencies on Qualcomm SA8775P
> platform. Also add LMH interrupts in cpufreq_hw
> node to indicate if there is any thermal throttle.
>
> The changes in this series are dependent on below series changes:
> https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@quicinc.com/
>
> [...]
Applied, thanks!
[1/2] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
(no commit info)
[2/2] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node
commit: cc13a858a79d8c5798a99e8cde677ea36272a5a0
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
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