linux-kernel - Re: MMIO and VERW

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Message-ID: <20250318165645.lnutevfmtld3vu4d@desk>
Date: Tue, 18 Mar 2025 09:56:45 -0700
From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To: Borislav Petkov <bp@...en8.de>
Cc: David Kaplan <david.kaplan@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Peter Zijlstra <peterz@...radead.org>,
	Josh Poimboeuf <jpoimboe@...nel.org>,
	Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
	"H . Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
	Brendan Jackman <jackmanb@...gle.com>,
	Derek Manwaring <derekmn@...zon.com>
Subject: Re: MMIO and VERW

On Tue, Mar 18, 2025 at 05:34:51PM +0100, Borislav Petkov wrote:
> On Tue, Mar 18, 2025 at 09:25:05AM -0700, Pawan Gupta wrote:
> > Rocket Lake, Comet Lake, Ice Lake with tsx=off only require VERW at
> > VMENTER. There are other MMIO affected CPUs that are not affected by MDS
> > and do not support TSX or disable it by default.
> 
> So all those CPUs are only affected by MMIO and not affected by neither of
> those:
> 
> TAA, RFDS, MDS

That is correct, they are not affected by MDS, TAA and RFDS.

> Or is that the case only when TSX is not enabled/not present there?

As per the affected CPU table [1], Ice Lake is not affected by TAA even if
TSX is enabled.

[1] https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html#tab-blade-1-2