linux-kernel - Re: MMIO and VERW

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Message-ID: <20250318173708.GFZ9mvROyNagmhawEV@fat_crate.local>
Date: Tue, 18 Mar 2025 18:37:08 +0100
From: Borislav Petkov <bp@...en8.de>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Cc: David Kaplan <david.kaplan@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Peter Zijlstra <peterz@...radead.org>,
	Josh Poimboeuf <jpoimboe@...nel.org>,
	Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
	"H . Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
	Brendan Jackman <jackmanb@...gle.com>,
	Derek Manwaring <derekmn@...zon.com>
Subject: Re: MMIO and VERW

On Tue, Mar 18, 2025 at 09:56:45AM -0700, Pawan Gupta wrote:
> On Tue, Mar 18, 2025 at 05:34:51PM +0100, Borislav Petkov wrote:
> > On Tue, Mar 18, 2025 at 09:25:05AM -0700, Pawan Gupta wrote:
> > > Rocket Lake, Comet Lake, Ice Lake with tsx=off only require VERW at
> > > VMENTER. There are other MMIO affected CPUs that are not affected by MDS
> > > and do not support TSX or disable it by default.
> > 
> > So all those CPUs are only affected by MMIO and not affected by neither of
> > those:
> > 
> > TAA, RFDS, MDS
> 
> That is correct, they are not affected by MDS, TAA and RFDS.
> 
> > Or is that the case only when TSX is not enabled/not present there?
> 
> As per the affected CPU table [1], Ice Lake is not affected by TAA even if
> TSX is enabled.

That table is insane - I need at least 4 monitors to stare at it properly. :-P

Anyway, so I'm wondering if we special-case those CPUs and have them select
a special

MMIO_MITIGATION_VERW_VM

case and keep them separate from that whole
CPUs-can-be-affected-by-multiple-vulns and the mitigation for all of them is
VERW.

They will enable mmio_stale_data_clear and will be out of the equation.

Which will make this other logic simpler.

Hmm...

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette