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Message-ID: <b62bd70e-691e-4b2b-a600-720d1f8ad12a@lunn.ch>
Date: Thu, 20 Mar 2025 22:27:46 +0100
From: Andrew Lunn <andrew@...n.ch>
To: hfdevel@....net
Cc: Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
FUJITA Tomonori <fujita.tomonori@...il.com>,
Andrew Lunn <andrew+netdev@...n.ch>, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next v6 6/7] net: tn40xx: prepare tn40xx driver to
find phy of the TN9510 card
On Tue, Mar 18, 2025 at 11:06:57PM +0100, Hans-Frieder Vogt via B4 Relay wrote:
> From: Hans-Frieder Vogt <hfdevel@....net>
>
> Prepare the tn40xx driver to load for Tehuti TN9510 cards, which require
> bit 3 in the register TN40_REG_MDIO_CMD_STAT to be set. The function of bit
> 3 is unclear, but may have something to do with the length of the preamble
> in the MDIO communication. If bit 3 is not set, the PHY will not be found
> when performing a scan for PHYs. Use the available tn40_mdio_set_speed
> function which includes setting bit 3. Just move the function to before the
> devm_mdio_register function, which scans the mdio bus for PHYs.
It might also have something to do with the bus speed. 802.3 says the
MDIO bus should be clocked only up to 2.5Mhz. Some MDIO devices do
work faster than that. So it could be the hardware defaults to
something very fast. By setting it to 6MHZ, you might be slowing it
down to speed which the aquantia PHY and board layout supports.
All just speculation, and does not stop getting the patch merged.
Andrew
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