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Message-ID: <uenisk2rrlx5sh6xagd7texx3dpxyav6yxpqxmk3fcdq44vb75@tk3pimdajilb>
Date: Mon, 24 Mar 2025 13:22:56 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: george.moussalem@...look.com
Cc: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Nitheesh Sekar <quic_nsekar@...cinc.com>, Varadarajan Narayanan <quic_varada@...cinc.com>,
Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
20250317100029.881286-2-quic_varada@...cinc.com, Sricharan Ramabadhran <quic_srichara@...cinc.com>
Subject: Re: [PATCH v6 3/6] dt-bindings: PCI: qcom: Add IPQ5018 SoC
On Fri, Mar 21, 2025 at 04:14:41PM +0400, George Moussalem via B4 Relay wrote:
> From: Nitheesh Sekar <quic_nsekar@...cinc.com>
>
> Add support for the PCIe controller on the Qualcomm
> IPQ5108 SoC to the bindings.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
- Mani
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 469b99fa0f0e..668ff03f2561 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -21,6 +21,7 @@ properties:
> - qcom,pcie-apq8064
> - qcom,pcie-apq8084
> - qcom,pcie-ipq4019
> + - qcom,pcie-ipq5018
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064-v2
> @@ -168,6 +169,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-ipq5018
> - qcom,pcie-ipq6018
> - qcom,pcie-ipq8074-gen3
> - qcom,pcie-ipq9574
> @@ -324,6 +326,53 @@ allOf:
> - const: ahb # AHB reset
> - const: phy_ahb # PHY AHB reset
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq5018
> + then:
> + properties:
> + clocks:
> + minItems: 6
> + maxItems: 6
> + clock-names:
> + items:
> + - const: iface # PCIe to SysNOC BIU clock
> + - const: axi_m # AXI Master clock
> + - const: axi_s # AXI Slave clock
> + - const: ahb # AHB clock
> + - const: aux # Auxiliary clock
> + - const: axi_bridge # AXI bridge clock
> + resets:
> + minItems: 8
> + maxItems: 8
> + reset-names:
> + items:
> + - const: pipe # PIPE reset
> + - const: sleep # Sleep reset
> + - const: sticky # Core sticky reset
> + - const: axi_m # AXI master reset
> + - const: axi_s # AXI slave reset
> + - const: ahb # AHB reset
> + - const: axi_m_sticky # AXI master sticky reset
> + - const: axi_s_sticky # AXI slave sticky reset
> + interrupts:
> + minItems: 9
> + maxItems: 9
> + interrupt-names:
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> + - const: global
> +
> - if:
> properties:
> compatible:
> @@ -564,6 +613,7 @@ allOf:
> enum:
> - qcom,pcie-apq8064
> - qcom,pcie-ipq4019
> + - qcom,pcie-ipq5018
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064v2
> - qcom,pcie-ipq8074
>
> --
> 2.48.1
>
>
--
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